2 * Copyright (c) 2014 Google, Inc
4 * Graeme Russ, graeme.russ@gmail.com.
6 * Some portions from coreboot src/mainboard/google/link/romstage.c
7 * Copyright (C) 2007-2010 coresystems GmbH
8 * Copyright (C) 2011 Google Inc.
10 * SPDX-License-Identifier: GPL-2.0
22 #include <asm/processor.h>
23 #include <asm/arch/model_206ax.h>
24 #include <asm/arch/pch.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev)
30 /* Enable port 80 POST on LPC */
31 pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
32 clrbits_le32(RCB_REG(GCS), 4);
36 * Enable Prefetching and Caching.
38 static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev)
42 pci_hose_read_config_byte(hose, dev, 0xdc, ®8);
44 reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
45 pci_hose_write_config_byte(hose, dev, 0xdc, reg8);
48 static void set_var_mtrr(
49 unsigned reg, unsigned base, unsigned size, unsigned type)
52 /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
53 /* FIXME: It only support 4G less range */
54 wrmsr(MTRRphysBase_MSR(reg), base | type, 0);
55 wrmsr(MTRRphysMask_MSR(reg), ~(size - 1) | MTRRphysMaskValid,
56 (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1);
59 static void enable_rom_caching(void)
62 set_var_mtrr(1, 0xffc00000, 4 << 20, MTRR_TYPE_WRPROT);
65 /* Enable Variable MTRRs */
66 wrmsr(MTRRdefType_MSR, 0x800, 0);
69 static int set_flex_ratio_to_tdp_nominal(void)
71 msr_t flex_ratio, msr;
74 /* Minimum CPU revision for configurable TDP support */
75 if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
78 /* Check for Flex Ratio support */
79 flex_ratio = msr_read(MSR_FLEX_RATIO);
80 if (!(flex_ratio.lo & FLEX_RATIO_EN))
83 /* Check for >0 configurable TDPs */
84 msr = msr_read(MSR_PLATFORM_INFO);
85 if (((msr.hi >> 1) & 3) == 0)
88 /* Use nominal TDP ratio for flex ratio */
89 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
90 nominal_ratio = msr.lo & 0xff;
92 /* See if flex ratio is already set to nominal TDP ratio */
93 if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
96 /* Set flex ratio to nominal TDP ratio */
97 flex_ratio.lo &= ~0xff00;
98 flex_ratio.lo |= nominal_ratio << 8;
99 flex_ratio.lo |= FLEX_RATIO_LOCK;
100 msr_write(MSR_FLEX_RATIO, flex_ratio);
102 /* Set flex ratio in soft reset data register bits 11:6 */
103 clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
104 (nominal_ratio & 0x3f) << 6);
106 /* Set soft reset control to use register value */
107 setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
109 /* Issue warm reset, will be "CPU only" due to soft reset data */
110 outb(0x0, PORT_RESET);
111 outb(0x6, PORT_RESET);
118 static void set_spi_speed(void)
122 /* Observe SPI Descriptor Component Section 0 */
123 writel(0x1000, RCB_REG(SPI_DESC_COMP0));
125 /* Extract the1 Write/Erase SPI Frequency from descriptor */
126 fdod = readl(RCB_REG(SPI_FREQ_WR_ERA));
130 /* Set Software Sequence frequency to match */
131 clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
134 int arch_cpu_init(void)
136 const void *blob = gd->fdt_blob;
137 struct pci_controller *hose;
141 post_code(POST_CPU_INIT);
142 timer_set_base(rdtsc());
144 ret = x86_cpu_init_f();
148 ret = pci_early_init_hose(&hose);
152 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
155 ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV);
159 enable_spi_prefetch(hose, PCH_LPC_DEV);
161 /* This is already done in start.S, but let's do it in C */
162 enable_port80_on_lpc(hose, PCH_LPC_DEV);
164 /* already done in car.S */
166 enable_rom_caching();
171 * We should do as little as possible before the serial console is
172 * up. Perhaps this should move to later. Our next lot of init
173 * happens in print_cpuinfo() when we have a console
175 ret = set_flex_ratio_to_tdp_nominal();
182 static int report_bist_failure(void)
184 if (gd->arch.bist != 0) {
185 printf("BIST failed: %08x\n", gd->arch.bist);
192 int print_cpuinfo(void)
194 char processor_name[CPU_MAX_NAME_LEN];
198 /* Halt if there was a built in self test failure */
199 ret = report_bist_failure();
203 /* Print processor name */
204 name = cpu_get_name(processor_name);
205 printf("CPU: %s\n", name);