2 * From Coreboot src/southbridge/intel/bd82x6x/early_me.c
4 * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
6 * SPDX-License-Identifier: GPL-2.0
12 #include <asm/processor.h>
13 #include <asm/arch/me.h>
14 #include <asm/arch/pch.h>
17 static const char *const me_ack_values[] = {
18 [ME_HFS_ACK_NO_DID] = "No DID Ack received",
19 [ME_HFS_ACK_RESET] = "Non-power cycle reset",
20 [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset",
21 [ME_HFS_ACK_S3] = "Go to S3",
22 [ME_HFS_ACK_S4] = "Go to S4",
23 [ME_HFS_ACK_S5] = "Go to S5",
24 [ME_HFS_ACK_GBL_RESET] = "Global Reset",
25 [ME_HFS_ACK_CONTINUE] = "Continue to boot"
28 static inline void pci_read_dword_ptr(void *ptr, int offset)
32 dword = pci_read_config32(PCH_ME_DEV, offset);
33 memcpy(ptr, &dword, sizeof(dword));
36 static inline void pci_write_dword_ptr(void *ptr, int offset)
39 memcpy(&dword, ptr, sizeof(dword));
40 pci_write_config32(PCH_ME_DEV, offset, dword);
43 void intel_early_me_status(void)
48 pci_read_dword_ptr(&hfs, PCI_ME_HFS);
49 pci_read_dword_ptr(&gmes, PCI_ME_GMES);
51 intel_me_status(&hfs, &gmes);
54 int intel_early_me_init(void)
60 debug("Intel ME early init\n");
62 /* Wait for ME UMA SIZE VALID bit to be set */
63 for (count = ME_RETRY; count > 0; --count) {
64 pci_read_dword_ptr(&uma, PCI_ME_UMA);
70 printf("ERROR: ME is not ready!\n");
74 /* Check for valid firmware */
75 pci_read_dword_ptr(&hfs, PCI_ME_HFS);
77 printf("WARNING: ME has bad firmware\n");
81 debug("Intel ME firmware is ready\n");
86 int intel_early_me_uma_size(void)
90 pci_read_dword_ptr(&uma, PCI_ME_UMA);
92 debug("ME: Requested %uMB UMA\n", uma.size);
96 debug("ME: Invalid UMA size\n");
100 static inline void set_global_reset(int enable)
104 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
106 /* Clear CF9 Without Resume Well Reset Enable */
107 etr3 &= ~ETR3_CWORWRE;
109 /* CF9GR indicates a Global Reset */
115 pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
118 int intel_early_me_init_done(u8 status)
122 u32 mebase_l, mebase_h;
124 struct me_did did = {
125 .init_done = ME_INIT_DONE,
129 /* MEBASE from MESEG_BASE[35:20] */
130 mebase_l = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L);
131 mebase_h = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H);
133 did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
135 /* Send message to ME */
136 debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n",
137 status, did.uma_base);
139 pci_write_dword_ptr(&did, PCI_ME_H_GS);
141 /* Must wait for ME acknowledgement */
142 for (count = ME_RETRY; count > 0; --count) {
143 pci_read_dword_ptr(&hfs, PCI_ME_HFS);
144 if (hfs.bios_msg_ack)
149 printf("ERROR: ME failed to respond\n");
153 /* Return the requested BIOS action */
154 debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);
156 /* Check status after acknowledgement */
157 intel_early_me_status();
160 switch (hfs.ack_data) {
161 case ME_HFS_ACK_CONTINUE:
162 /* Continue to boot */
164 case ME_HFS_ACK_RESET:
165 /* Non-power cycle reset */
169 case ME_HFS_ACK_PWR_CYCLE:
170 /* Power cycle reset */
174 case ME_HFS_ACK_GBL_RESET:
185 /* Perform the requested reset */