2 * From Coreboot src/southbridge/intel/bd82x6x/early_me.c
4 * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
6 * SPDX-License-Identifier: GPL-2.0
14 #include <asm/processor.h>
15 #include <asm/arch/me.h>
16 #include <asm/arch/pch.h>
19 static const char *const me_ack_values[] = {
20 [ME_HFS_ACK_NO_DID] = "No DID Ack received",
21 [ME_HFS_ACK_RESET] = "Non-power cycle reset",
22 [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset",
23 [ME_HFS_ACK_S3] = "Go to S3",
24 [ME_HFS_ACK_S4] = "Go to S4",
25 [ME_HFS_ACK_S5] = "Go to S5",
26 [ME_HFS_ACK_GBL_RESET] = "Global Reset",
27 [ME_HFS_ACK_CONTINUE] = "Continue to boot"
30 int intel_early_me_init(struct udevice *me_dev)
36 debug("Intel ME early init\n");
38 /* Wait for ME UMA SIZE VALID bit to be set */
39 for (count = ME_RETRY; count > 0; --count) {
40 pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA);
46 printf("ERROR: ME is not ready!\n");
50 /* Check for valid firmware */
51 pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
53 printf("WARNING: ME has bad firmware\n");
57 debug("Intel ME firmware is ready\n");
62 int intel_early_me_uma_size(struct udevice *me_dev)
66 pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA);
68 debug("ME: Requested %uMB UMA\n", uma.size);
72 debug("ME: Invalid UMA size\n");
76 static inline void set_global_reset(struct udevice *dev, int enable)
80 dm_pci_read_config32(dev, ETR3, &etr3);
82 /* Clear CF9 Without Resume Well Reset Enable */
83 etr3 &= ~ETR3_CWORWRE;
85 /* CF9GR indicates a Global Reset */
91 dm_pci_write_config32(dev, ETR3, etr3);
94 int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
98 u32 mebase_l, mebase_h;
100 struct me_did did = {
101 .init_done = ME_INIT_DONE,
105 /* MEBASE from MESEG_BASE[35:20] */
106 dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L, &mebase_l);
107 dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H, &mebase_h);
109 did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
111 /* Send message to ME */
112 debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n",
113 status, did.uma_base);
115 pci_write_dword_ptr(me_dev, &did, PCI_ME_H_GS);
117 /* Must wait for ME acknowledgement */
118 for (count = ME_RETRY; count > 0; --count) {
119 pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
120 if (hfs.bios_msg_ack)
125 printf("ERROR: ME failed to respond\n");
129 /* Return the requested BIOS action */
130 debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);
132 /* Check status after acknowledgement */
133 intel_me_status(me_dev);
135 switch (hfs.ack_data) {
136 case ME_HFS_ACK_CONTINUE:
137 /* Continue to boot */
139 case ME_HFS_ACK_RESET:
140 /* Non-power cycle reset */
141 set_global_reset(dev, 0);
144 case ME_HFS_ACK_PWR_CYCLE:
145 /* Power cycle reset */
146 set_global_reset(dev, 0);
149 case ME_HFS_ACK_GBL_RESET:
151 set_global_reset(dev, 1);
163 static const struct udevice_id ivybridge_syscon_ids[] = {
164 { .compatible = "intel,me", .data = X86_SYSCON_ME },
165 { .compatible = "intel,gma", .data = X86_SYSCON_GMA },
169 U_BOOT_DRIVER(syscon_intel_me) = {
170 .name = "intel_me_syscon",
172 .of_match = ivybridge_syscon_ids,