2 * From Coreboot src/southbridge/intel/bd82x6x/early_me.c
4 * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
6 * SPDX-License-Identifier: GPL-2.0
14 #include <asm/processor.h>
15 #include <asm/arch/me.h>
16 #include <asm/arch/pch.h>
19 static const char *const me_ack_values[] = {
20 [ME_HFS_ACK_NO_DID] = "No DID Ack received",
21 [ME_HFS_ACK_RESET] = "Non-power cycle reset",
22 [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset",
23 [ME_HFS_ACK_S3] = "Go to S3",
24 [ME_HFS_ACK_S4] = "Go to S4",
25 [ME_HFS_ACK_S5] = "Go to S5",
26 [ME_HFS_ACK_GBL_RESET] = "Global Reset",
27 [ME_HFS_ACK_CONTINUE] = "Continue to boot"
30 static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr,
35 dm_pci_read_config32(me_dev, offset, &dword);
36 memcpy(ptr, &dword, sizeof(dword));
39 static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr,
44 memcpy(&dword, ptr, sizeof(dword));
45 dm_pci_write_config32(me_dev, offset, dword);
48 void intel_early_me_status(struct udevice *me_dev)
53 pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
54 pci_read_dword_ptr(me_dev, &gmes, PCI_ME_GMES);
56 intel_me_status(&hfs, &gmes);
59 int intel_early_me_init(struct udevice *me_dev)
65 debug("Intel ME early init\n");
67 /* Wait for ME UMA SIZE VALID bit to be set */
68 for (count = ME_RETRY; count > 0; --count) {
69 pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA);
75 printf("ERROR: ME is not ready!\n");
79 /* Check for valid firmware */
80 pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
82 printf("WARNING: ME has bad firmware\n");
86 debug("Intel ME firmware is ready\n");
91 int intel_early_me_uma_size(struct udevice *me_dev)
95 pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA);
97 debug("ME: Requested %uMB UMA\n", uma.size);
101 debug("ME: Invalid UMA size\n");
105 static inline void set_global_reset(struct udevice *dev, int enable)
109 dm_pci_read_config32(dev, ETR3, &etr3);
111 /* Clear CF9 Without Resume Well Reset Enable */
112 etr3 &= ~ETR3_CWORWRE;
114 /* CF9GR indicates a Global Reset */
120 dm_pci_write_config32(dev, ETR3, etr3);
123 int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
127 u32 mebase_l, mebase_h;
129 struct me_did did = {
130 .init_done = ME_INIT_DONE,
134 /* MEBASE from MESEG_BASE[35:20] */
135 dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L, &mebase_l);
136 dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H, &mebase_h);
138 did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
140 /* Send message to ME */
141 debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n",
142 status, did.uma_base);
144 pci_write_dword_ptr(me_dev, &did, PCI_ME_H_GS);
146 /* Must wait for ME acknowledgement */
147 for (count = ME_RETRY; count > 0; --count) {
148 pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
149 if (hfs.bios_msg_ack)
154 printf("ERROR: ME failed to respond\n");
158 /* Return the requested BIOS action */
159 debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);
161 /* Check status after acknowledgement */
162 intel_early_me_status(me_dev);
164 switch (hfs.ack_data) {
165 case ME_HFS_ACK_CONTINUE:
166 /* Continue to boot */
168 case ME_HFS_ACK_RESET:
169 /* Non-power cycle reset */
170 set_global_reset(dev, 0);
173 case ME_HFS_ACK_PWR_CYCLE:
174 /* Power cycle reset */
175 set_global_reset(dev, 0);
178 case ME_HFS_ACK_GBL_RESET:
180 set_global_reset(dev, 1);
192 static const struct udevice_id ivybridge_syscon_ids[] = {
193 { .compatible = "intel,me", .data = X86_SYSCON_ME },
197 U_BOOT_DRIVER(syscon_intel_me) = {
198 .name = "intel_me_syscon",
200 .of_match = ivybridge_syscon_ids,