2 * From Coreboot src/southbridge/intel/bd82x6x/early_me.c
4 * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
6 * SPDX-License-Identifier: GPL-2.0
13 #include <asm/processor.h>
14 #include <asm/arch/me.h>
15 #include <asm/arch/pch.h>
18 static const char *const me_ack_values[] = {
19 [ME_HFS_ACK_NO_DID] = "No DID Ack received",
20 [ME_HFS_ACK_RESET] = "Non-power cycle reset",
21 [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset",
22 [ME_HFS_ACK_S3] = "Go to S3",
23 [ME_HFS_ACK_S4] = "Go to S4",
24 [ME_HFS_ACK_S5] = "Go to S5",
25 [ME_HFS_ACK_GBL_RESET] = "Global Reset",
26 [ME_HFS_ACK_CONTINUE] = "Continue to boot"
29 static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr,
34 dm_pci_read_config32(me_dev, offset, &dword);
35 memcpy(ptr, &dword, sizeof(dword));
38 static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr,
43 memcpy(&dword, ptr, sizeof(dword));
44 dm_pci_write_config32(me_dev, offset, dword);
47 void intel_early_me_status(struct udevice *me_dev)
52 pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
53 pci_read_dword_ptr(me_dev, &gmes, PCI_ME_GMES);
55 intel_me_status(&hfs, &gmes);
58 int intel_early_me_init(struct udevice *me_dev)
64 debug("Intel ME early init\n");
66 /* Wait for ME UMA SIZE VALID bit to be set */
67 for (count = ME_RETRY; count > 0; --count) {
68 pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA);
74 printf("ERROR: ME is not ready!\n");
78 /* Check for valid firmware */
79 pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
81 printf("WARNING: ME has bad firmware\n");
85 debug("Intel ME firmware is ready\n");
90 int intel_early_me_uma_size(struct udevice *me_dev)
94 pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA);
96 debug("ME: Requested %uMB UMA\n", uma.size);
100 debug("ME: Invalid UMA size\n");
104 static inline void set_global_reset(struct udevice *dev, int enable)
108 dm_pci_read_config32(dev, ETR3, &etr3);
110 /* Clear CF9 Without Resume Well Reset Enable */
111 etr3 &= ~ETR3_CWORWRE;
113 /* CF9GR indicates a Global Reset */
119 dm_pci_write_config32(dev, ETR3, etr3);
122 int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
126 u32 mebase_l, mebase_h;
128 struct me_did did = {
129 .init_done = ME_INIT_DONE,
133 /* MEBASE from MESEG_BASE[35:20] */
134 dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L, &mebase_l);
135 dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H, &mebase_h);
137 did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
139 /* Send message to ME */
140 debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n",
141 status, did.uma_base);
143 pci_write_dword_ptr(me_dev, &did, PCI_ME_H_GS);
145 /* Must wait for ME acknowledgement */
146 for (count = ME_RETRY; count > 0; --count) {
147 pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
148 if (hfs.bios_msg_ack)
153 printf("ERROR: ME failed to respond\n");
157 /* Return the requested BIOS action */
158 debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);
160 /* Check status after acknowledgement */
161 intel_early_me_status(me_dev);
163 switch (hfs.ack_data) {
164 case ME_HFS_ACK_CONTINUE:
165 /* Continue to boot */
167 case ME_HFS_ACK_RESET:
168 /* Non-power cycle reset */
169 set_global_reset(dev, 0);
172 case ME_HFS_ACK_PWR_CYCLE:
173 /* Power cycle reset */
174 set_global_reset(dev, 0);
177 case ME_HFS_ACK_GBL_RESET:
179 set_global_reset(dev, 1);
191 static const struct udevice_id ivybridge_syscon_ids[] = {
192 { .compatible = "intel,me", },
196 U_BOOT_DRIVER(syscon_intel_me) = {
197 .name = "intel_me_syscon",
199 .of_match = ivybridge_syscon_ids,