2 * From coreboot southbridge/intel/bd82x6x/lpc.c
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * SPDX-License-Identifier: GPL-2.0
15 #include <asm/interrupt.h>
17 #include <asm/ioapic.h>
19 #include <asm/arch/pch.h>
23 #define ENABLE_ACPI_MODE_IN_COREBOOT 0
24 #define TEST_SMM_FLASH_LOCKDOWN 0
26 static int pch_enable_apic(pci_dev_t dev)
31 /* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */
32 pci_write_config8(dev, ACPI_CNTL, 0x80);
34 writel(0, IO_APIC_INDEX);
35 writel(1 << 25, IO_APIC_DATA);
37 /* affirm full set of redirection table entries ("write once") */
38 writel(1, IO_APIC_INDEX);
39 reg32 = readl(IO_APIC_DATA);
40 writel(1, IO_APIC_INDEX);
41 writel(reg32, IO_APIC_DATA);
43 writel(0, IO_APIC_INDEX);
44 reg32 = readl(IO_APIC_DATA);
45 debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f);
46 if (reg32 != (1 << 25)) {
47 printf("APIC Error - cannot write to registers\n");
51 debug("Dumping IOAPIC registers\n");
52 for (i = 0; i < 3; i++) {
53 writel(i, IO_APIC_INDEX);
54 debug(" reg 0x%04x:", i);
55 reg32 = readl(IO_APIC_DATA);
56 debug(" 0x%08x\n", reg32);
59 /* Select Boot Configuration register. */
60 writel(3, IO_APIC_INDEX);
62 /* Use Processor System Bus to deliver interrupts. */
63 writel(1, IO_APIC_DATA);
68 static void pch_enable_serial_irqs(pci_dev_t dev)
72 /* Set packet length and toggle silent mode bit for one frame. */
73 value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0);
74 #ifdef CONFIG_SERIRQ_CONTINUOUS_MODE
75 pci_write_config8(dev, SERIRQ_CNTL, value);
77 pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6));
81 static int pch_pirq_init(const void *blob, int node, pci_dev_t dev)
83 uint8_t route[8], *ptr;
85 if (fdtdec_get_byte_array(blob, node, "intel,pirq-routing", route,
89 pci_write_config8(dev, PIRQA_ROUT, *ptr++);
90 pci_write_config8(dev, PIRQB_ROUT, *ptr++);
91 pci_write_config8(dev, PIRQC_ROUT, *ptr++);
92 pci_write_config8(dev, PIRQD_ROUT, *ptr++);
94 pci_write_config8(dev, PIRQE_ROUT, *ptr++);
95 pci_write_config8(dev, PIRQF_ROUT, *ptr++);
96 pci_write_config8(dev, PIRQG_ROUT, *ptr++);
97 pci_write_config8(dev, PIRQH_ROUT, *ptr++);
100 * TODO(sjg@chromium.org): U-Boot does not set up the interrupts
101 * here. It's unclear if it is needed
106 static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev)
112 if (fdtdec_get_byte_array(blob, node, "intel,gpi-routing", route,
116 for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++)
117 reg |= route[gpi] << (gpi * 2);
119 pci_write_config32(dev, 0xb8, reg);
124 static int pch_power_options(const void *blob, int node, pci_dev_t dev)
135 * Which state do we want to goto after g3 (power restored)?
139 * If the option is not existent (Laptops), use Kconfig setting.
140 * TODO(sjg@chromium.org): Make this configurable
142 pwr_on = MAINBOARD_POWER_ON;
144 reg16 = pci_read_config16(dev, GEN_PMCON_3);
147 case MAINBOARD_POWER_OFF:
151 case MAINBOARD_POWER_ON:
155 case MAINBOARD_POWER_KEEP:
157 state = "state keep";
163 reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
164 reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
167 reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
169 reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
171 pci_write_config16(dev, GEN_PMCON_3, reg16);
172 debug("Set power %s after power failure.\n", state);
174 /* Set up NMI on errors. */
176 reg8 &= 0x0f; /* Higher Nibble must be 0 */
177 reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
178 reg8 |= (1 << 2); /* PCI SERR# Disable for now */
182 /* TODO(sjg@chromium.org): Make this configurable */
183 nmi_option = NMI_OFF;
185 debug("NMI sources enabled.\n");
186 reg8 &= ~(1 << 7); /* Set NMI. */
188 debug("NMI sources disabled.\n");
189 /* Can't mask NMI from PCI-E and NMI_NOW */
194 /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
195 reg16 = pci_read_config16(dev, GEN_PMCON_1);
196 reg16 &= ~(3 << 0); /* SMI# rate 1 minute */
197 reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
198 #if DEBUG_PERIODIC_SMIS
199 /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */
200 reg16 |= (3 << 0); /* Periodic SMI every 8s */
202 pci_write_config16(dev, GEN_PMCON_1, reg16);
204 /* Set the board's GPI routing. */
205 ret = pch_gpi_routing(blob, node, dev);
209 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
211 writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
212 "intel,gpe0-enable", 0));
213 writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node,
214 "intel,alt-gp-smi-enable", 0));
216 /* Set up power management block and determine sleep mode */
217 reg32 = inl(pmbase + 0x04); /* PM1_CNT */
218 reg32 &= ~(7 << 10); /* SLP_TYP */
219 reg32 |= (1 << 0); /* SCI_EN */
220 outl(reg32, pmbase + 0x04);
222 /* Clear magic status bits to prevent unexpected wake */
223 setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0));
224 clrbits_le32(RCB_REG(0x3f02), 0xf);
229 static void pch_rtc_init(pci_dev_t dev)
234 reg8 = pci_read_config8(dev, GEN_PMCON_3);
235 rtc_failed = reg8 & RTC_BATTERY_DEAD;
237 reg8 &= ~RTC_BATTERY_DEAD;
238 pci_write_config8(dev, GEN_PMCON_3, reg8);
240 debug("rtc_failed = 0x%x\n", rtc_failed);
242 #if CONFIG_HAVE_ACPI_RESUME
243 /* Avoid clearing pending interrupts and resetting the RTC control
244 * register in the resume path because the Linux kernel relies on
245 * this to know if it should restart the RTC timerqueue if the wake
246 * was due to the RTC alarm.
248 if (acpi_get_slp_type() == 3)
251 /* TODO: Handle power failure */
253 printf("RTC power failed\n");
257 /* CougarPoint PCH Power Management init */
258 static void cpt_pm_init(pci_dev_t dev)
260 debug("CougarPoint PM init\n");
261 pci_write_config8(dev, 0xa9, 0x47);
262 setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));
264 setbits_le32(RCB_REG(0x228c), 1 << 0);
265 setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14));
266 setbits_le32(RCB_REG(0x0900), 1 << 14);
267 writel(0xc0388400, RCB_REG(0x2304));
268 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
269 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
270 clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf);
271 writel(0x050f0000, RCB_REG(0x3318));
272 writel(0x04000000, RCB_REG(0x3324));
273 setbits_le32(RCB_REG(0x3340), 0xfffff);
274 setbits_le32(RCB_REG(0x3344), 1 << 1);
276 writel(0x0001c000, RCB_REG(0x3360));
277 writel(0x00061100, RCB_REG(0x3368));
278 writel(0x7f8fdfff, RCB_REG(0x3378));
279 writel(0x000003fc, RCB_REG(0x337c));
280 writel(0x00001000, RCB_REG(0x3388));
281 writel(0x0001c000, RCB_REG(0x3390));
282 writel(0x00000800, RCB_REG(0x33a0));
283 writel(0x00001000, RCB_REG(0x33b0));
284 writel(0x00093900, RCB_REG(0x33c0));
285 writel(0x24653002, RCB_REG(0x33cc));
286 writel(0x062108fe, RCB_REG(0x33d0));
287 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
288 writel(0x01010000, RCB_REG(0x3a28));
289 writel(0x01010404, RCB_REG(0x3a2c));
290 writel(0x01041041, RCB_REG(0x3a80));
291 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
292 setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */
293 setbits_le32(RCB_REG(0x3a88), 1 << 0); /* SATA 4/5 disabled */
294 writel(0x00000001, RCB_REG(0x3a6c));
295 clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c);
296 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
297 writel(0, RCB_REG(0x33c8));
298 setbits_le32(RCB_REG(0x21b0), 0xf);
301 /* PantherPoint PCH Power Management init */
302 static void ppt_pm_init(pci_dev_t dev)
304 debug("PantherPoint PM init\n");
305 pci_write_config8(dev, 0xa9, 0x47);
306 setbits_le32(RCB_REG(0x2238), 1 << 0);
307 setbits_le32(RCB_REG(0x228c), 1 << 0);
308 setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14));
309 setbits_le16(RCB_REG(0x0900), 1 << 14);
310 writel(0xc03b8400, RCB_REG(0x2304));
311 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
312 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
313 clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf);
314 writel(0x054f0000, RCB_REG(0x3318));
315 writel(0x04000000, RCB_REG(0x3324));
316 setbits_le32(RCB_REG(0x3340), 0xfffff);
317 setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0));
318 writel(0x0001c000, RCB_REG(0x3360));
319 writel(0x00061100, RCB_REG(0x3368));
320 writel(0x7f8fdfff, RCB_REG(0x3378));
321 writel(0x000003fd, RCB_REG(0x337c));
322 writel(0x00001000, RCB_REG(0x3388));
323 writel(0x0001c000, RCB_REG(0x3390));
324 writel(0x00000800, RCB_REG(0x33a0));
325 writel(0x00001000, RCB_REG(0x33b0));
326 writel(0x00093900, RCB_REG(0x33c0));
327 writel(0x24653002, RCB_REG(0x33cc));
328 writel(0x067388fe, RCB_REG(0x33d0));
329 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
330 writel(0x01010000, RCB_REG(0x3a28));
331 writel(0x01010404, RCB_REG(0x3a2c));
332 writel(0x01040000, RCB_REG(0x3a80));
333 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
334 /* SATA 2/3 disabled */
335 setbits_le32(RCB_REG(0x3a84), 1 << 24);
336 /* SATA 4/5 disabled */
337 setbits_le32(RCB_REG(0x3a88), 1 << 0);
338 writel(0x00000001, RCB_REG(0x3a6c));
339 clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c);
340 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
341 setbits_le32(RCB_REG(0x33a4), (1 << 0));
342 writel(0, RCB_REG(0x33c8));
343 setbits_le32(RCB_REG(0x21b0), 0xf);
346 static void enable_hpet(void)
348 /* Move HPET to default address 0xfed00000 and enable it */
349 clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7);
352 static void enable_clock_gating(pci_dev_t dev)
357 setbits_le32(RCB_REG(0x2234), 0xf);
359 reg16 = pci_read_config16(dev, GEN_PMCON_1);
360 reg16 |= (1 << 2) | (1 << 11);
361 pci_write_config16(dev, GEN_PMCON_1, reg16);
363 pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
364 pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
365 pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
366 pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
368 reg32 = readl(RCB_REG(CG));
370 reg32 |= (1 << 29) | (1 << 28);
371 reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
381 writel(reg32, RCB_REG(CG));
383 setbits_le32(RCB_REG(0x38c0), 0x7);
384 setbits_le32(RCB_REG(0x36d4), 0x6680c004);
385 setbits_le32(RCB_REG(0x3564), 0x3);
388 #if CONFIG_HAVE_SMI_HANDLER
389 static void pch_lock_smm(pci_dev_t dev)
391 #if TEST_SMM_FLASH_LOCKDOWN
395 if (acpi_slp_type != 3) {
396 #if ENABLE_ACPI_MODE_IN_COREBOOT
397 debug("Enabling ACPI via APMC:\n");
398 outb(0xe1, 0xb2); /* Enable ACPI mode */
401 debug("Disabling ACPI via APMC:\n");
402 outb(0x1e, 0xb2); /* Disable ACPI mode */
407 /* Don't allow evil boot loaders, kernels, or
408 * userspace applications to deceive us:
412 #if TEST_SMM_FLASH_LOCKDOWN
414 debug("Locking BIOS to RO... ");
415 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
416 debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
417 (reg8 & 1) ? "rw" : "ro");
418 reg8 &= ~(1 << 0); /* clear BIOSWE */
419 pci_write_config8(dev, 0xdc, reg8);
420 reg8 |= (1 << 1); /* set BLE */
421 pci_write_config8(dev, 0xdc, reg8);
423 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
424 debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
425 (reg8 & 1) ? "rw" : "ro");
428 writeb(0, 0xfff00000);
430 reg8 |= (1 << 0); /* set BIOSWE */
431 pci_write_config8(dev, 0xdc, reg8);
433 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
434 debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
435 (reg8 & 1) ? "rw" : "ro");
441 static void pch_disable_smm_only_flashing(pci_dev_t dev)
445 debug("Enabling BIOS updates outside of SMM... ");
446 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
448 pci_write_config8(dev, 0xdc, reg8);
451 static void pch_fixups(pci_dev_t dev)
455 /* Indicate DRAM init done for MRC S3 to know it can resume */
456 gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2);
457 gen_pmcon_2 |= (1 << 7);
458 pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
460 /* Enable DMI ASPM in the PCH */
461 clrbits_le32(RCB_REG(0x2304), 1 << 10);
462 setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10));
463 setbits_le32(RCB_REG(0x21a8), 0x3);
466 int lpc_early_init(const void *blob, int node, pci_dev_t dev)
475 count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec",
476 (u32 *)values, sizeof(values) / sizeof(u32));
480 /* Set COM1/COM2 decode range */
481 pci_write_config16(dev, LPC_IO_DEC, 0x0010);
483 /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
484 pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
485 GAMEL_LPC_EN | COMA_LPC_EN);
487 /* Write all registers but use 0 if we run out of data */
488 count = count * sizeof(u32) / sizeof(values[0]);
489 for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
493 reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
494 pci_write_config32(dev, LPC_GENX_DEC(i), reg);
500 int lpc_init(struct pci_controller *hose, pci_dev_t dev)
502 const void *blob = gd->fdt_blob;
505 debug("pch: lpc_init\n");
506 pci_write_bar32(hose, dev, 0, 0);
507 pci_write_bar32(hose, dev, 1, 0xff800000);
508 pci_write_bar32(hose, dev, 2, 0xfec00000);
509 pci_write_bar32(hose, dev, 3, 0x800);
510 pci_write_bar32(hose, dev, 4, 0x900);
512 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
516 /* Set the value for PCI command register. */
517 pci_write_config16(dev, PCI_COMMAND, 0x000f);
519 /* IO APIC initialization. */
520 pch_enable_apic(dev);
522 pch_enable_serial_irqs(dev);
524 /* Setup the PIRQ. */
525 pch_pirq_init(blob, node, dev);
527 /* Setup power options. */
528 pch_power_options(blob, node, dev);
530 /* Initialize power management */
531 switch (pch_silicon_type()) {
532 case PCH_TYPE_CPT: /* CougarPoint */
535 case PCH_TYPE_PPT: /* PantherPoint */
539 printf("Unknown Chipset: %#02x.%dx\n", PCI_DEV(dev),
544 /* Initialize the real time clock. */
547 /* Initialize the High Precision Event Timers, if present. */
550 /* Initialize Clock Gating */
551 enable_clock_gating(dev);
553 pch_disable_smm_only_flashing(dev);
555 #if CONFIG_HAVE_SMI_HANDLER
564 void lpc_enable(pci_dev_t dev)
566 /* Enable PCH Display Port */
567 writew(0x0010, RCB_REG(DISPBDF));
568 setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);