2 * From coreboot southbridge/intel/bd82x6x/lpc.c
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * SPDX-License-Identifier: GPL-2.0
14 #include <asm/arch/pch.h>
16 int lpc_early_init(const void *blob, int node, pci_dev_t dev)
25 count = fdtdec_get_int_array_count(blob, node, "gen-dec",
26 (u32 *)values, sizeof(values) / sizeof(u32));
30 /* Set COM1/COM2 decode range */
31 pci_write_config16(dev, LPC_IO_DEC, 0x0010);
33 /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
34 pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
35 GAMEL_LPC_EN | COMA_LPC_EN);
37 /* Write all registers but use 0 if we run out of data */
38 count = count * sizeof(u32) / sizeof(values[0]);
39 for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
43 reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
44 pci_write_config32(dev, LPC_GENX_DEC(i), reg);