2 * From coreboot southbridge/intel/bd82x6x/lpc.c
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * SPDX-License-Identifier: GPL-2.0
16 #include <asm/interrupt.h>
18 #include <asm/ioapic.h>
20 #include <asm/arch/pch.h>
24 #define ENABLE_ACPI_MODE_IN_COREBOOT 0
25 #define TEST_SMM_FLASH_LOCKDOWN 0
27 static int pch_enable_apic(pci_dev_t dev)
32 /* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */
33 x86_pci_write_config8(dev, ACPI_CNTL, 0x80);
35 writel(0, IO_APIC_INDEX);
36 writel(1 << 25, IO_APIC_DATA);
38 /* affirm full set of redirection table entries ("write once") */
39 writel(1, IO_APIC_INDEX);
40 reg32 = readl(IO_APIC_DATA);
41 writel(1, IO_APIC_INDEX);
42 writel(reg32, IO_APIC_DATA);
44 writel(0, IO_APIC_INDEX);
45 reg32 = readl(IO_APIC_DATA);
46 debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f);
47 if (reg32 != (1 << 25)) {
48 printf("APIC Error - cannot write to registers\n");
52 debug("Dumping IOAPIC registers\n");
53 for (i = 0; i < 3; i++) {
54 writel(i, IO_APIC_INDEX);
55 debug(" reg 0x%04x:", i);
56 reg32 = readl(IO_APIC_DATA);
57 debug(" 0x%08x\n", reg32);
60 /* Select Boot Configuration register. */
61 writel(3, IO_APIC_INDEX);
63 /* Use Processor System Bus to deliver interrupts. */
64 writel(1, IO_APIC_DATA);
69 static void pch_enable_serial_irqs(pci_dev_t dev)
73 /* Set packet length and toggle silent mode bit for one frame. */
74 value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0);
75 #ifdef CONFIG_SERIRQ_CONTINUOUS_MODE
76 x86_pci_write_config8(dev, SERIRQ_CNTL, value);
78 x86_pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6));
82 static int pch_pirq_init(const void *blob, int node, pci_dev_t dev)
84 uint8_t route[8], *ptr;
86 if (fdtdec_get_byte_array(blob, node, "intel,pirq-routing", route,
90 x86_pci_write_config8(dev, PIRQA_ROUT, *ptr++);
91 x86_pci_write_config8(dev, PIRQB_ROUT, *ptr++);
92 x86_pci_write_config8(dev, PIRQC_ROUT, *ptr++);
93 x86_pci_write_config8(dev, PIRQD_ROUT, *ptr++);
95 x86_pci_write_config8(dev, PIRQE_ROUT, *ptr++);
96 x86_pci_write_config8(dev, PIRQF_ROUT, *ptr++);
97 x86_pci_write_config8(dev, PIRQG_ROUT, *ptr++);
98 x86_pci_write_config8(dev, PIRQH_ROUT, *ptr++);
101 * TODO(sjg@chromium.org): U-Boot does not set up the interrupts
102 * here. It's unclear if it is needed
107 static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev)
113 if (fdtdec_get_byte_array(blob, node, "intel,gpi-routing", route,
117 for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++)
118 reg |= route[gpi] << (gpi * 2);
120 x86_pci_write_config32(dev, 0xb8, reg);
125 static int pch_power_options(const void *blob, int node, pci_dev_t dev)
136 * Which state do we want to goto after g3 (power restored)?
140 * If the option is not existent (Laptops), use Kconfig setting.
141 * TODO(sjg@chromium.org): Make this configurable
143 pwr_on = MAINBOARD_POWER_ON;
145 reg16 = x86_pci_read_config16(dev, GEN_PMCON_3);
148 case MAINBOARD_POWER_OFF:
152 case MAINBOARD_POWER_ON:
156 case MAINBOARD_POWER_KEEP:
158 state = "state keep";
164 reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
165 reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
168 reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
170 reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
172 x86_pci_write_config16(dev, GEN_PMCON_3, reg16);
173 debug("Set power %s after power failure.\n", state);
175 /* Set up NMI on errors. */
177 reg8 &= 0x0f; /* Higher Nibble must be 0 */
178 reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
179 reg8 |= (1 << 2); /* PCI SERR# Disable for now */
183 /* TODO(sjg@chromium.org): Make this configurable */
184 nmi_option = NMI_OFF;
186 debug("NMI sources enabled.\n");
187 reg8 &= ~(1 << 7); /* Set NMI. */
189 debug("NMI sources disabled.\n");
190 /* Can't mask NMI from PCI-E and NMI_NOW */
195 /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
196 reg16 = x86_pci_read_config16(dev, GEN_PMCON_1);
197 reg16 &= ~(3 << 0); /* SMI# rate 1 minute */
198 reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
199 #if DEBUG_PERIODIC_SMIS
200 /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */
201 reg16 |= (3 << 0); /* Periodic SMI every 8s */
203 x86_pci_write_config16(dev, GEN_PMCON_1, reg16);
205 /* Set the board's GPI routing. */
206 ret = pch_gpi_routing(blob, node, dev);
210 pmbase = x86_pci_read_config16(dev, 0x40) & 0xfffe;
212 writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
213 "intel,gpe0-enable", 0));
214 writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node,
215 "intel,alt-gp-smi-enable", 0));
217 /* Set up power management block and determine sleep mode */
218 reg32 = inl(pmbase + 0x04); /* PM1_CNT */
219 reg32 &= ~(7 << 10); /* SLP_TYP */
220 reg32 |= (1 << 0); /* SCI_EN */
221 outl(reg32, pmbase + 0x04);
223 /* Clear magic status bits to prevent unexpected wake */
224 setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0));
225 clrbits_le32(RCB_REG(0x3f02), 0xf);
230 static void pch_rtc_init(pci_dev_t dev)
235 reg8 = x86_pci_read_config8(dev, GEN_PMCON_3);
236 rtc_failed = reg8 & RTC_BATTERY_DEAD;
238 reg8 &= ~RTC_BATTERY_DEAD;
239 x86_pci_write_config8(dev, GEN_PMCON_3, reg8);
241 debug("rtc_failed = 0x%x\n", rtc_failed);
243 #if CONFIG_HAVE_ACPI_RESUME
244 /* Avoid clearing pending interrupts and resetting the RTC control
245 * register in the resume path because the Linux kernel relies on
246 * this to know if it should restart the RTC timerqueue if the wake
247 * was due to the RTC alarm.
249 if (acpi_get_slp_type() == 3)
252 /* TODO: Handle power failure */
254 printf("RTC power failed\n");
258 /* CougarPoint PCH Power Management init */
259 static void cpt_pm_init(pci_dev_t dev)
261 debug("CougarPoint PM init\n");
262 x86_pci_write_config8(dev, 0xa9, 0x47);
263 setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));
265 setbits_le32(RCB_REG(0x228c), 1 << 0);
266 setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14));
267 setbits_le32(RCB_REG(0x0900), 1 << 14);
268 writel(0xc0388400, RCB_REG(0x2304));
269 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
270 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
271 clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf);
272 writel(0x050f0000, RCB_REG(0x3318));
273 writel(0x04000000, RCB_REG(0x3324));
274 setbits_le32(RCB_REG(0x3340), 0xfffff);
275 setbits_le32(RCB_REG(0x3344), 1 << 1);
277 writel(0x0001c000, RCB_REG(0x3360));
278 writel(0x00061100, RCB_REG(0x3368));
279 writel(0x7f8fdfff, RCB_REG(0x3378));
280 writel(0x000003fc, RCB_REG(0x337c));
281 writel(0x00001000, RCB_REG(0x3388));
282 writel(0x0001c000, RCB_REG(0x3390));
283 writel(0x00000800, RCB_REG(0x33a0));
284 writel(0x00001000, RCB_REG(0x33b0));
285 writel(0x00093900, RCB_REG(0x33c0));
286 writel(0x24653002, RCB_REG(0x33cc));
287 writel(0x062108fe, RCB_REG(0x33d0));
288 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
289 writel(0x01010000, RCB_REG(0x3a28));
290 writel(0x01010404, RCB_REG(0x3a2c));
291 writel(0x01041041, RCB_REG(0x3a80));
292 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
293 setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */
294 setbits_le32(RCB_REG(0x3a88), 1 << 0); /* SATA 4/5 disabled */
295 writel(0x00000001, RCB_REG(0x3a6c));
296 clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c);
297 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
298 writel(0, RCB_REG(0x33c8));
299 setbits_le32(RCB_REG(0x21b0), 0xf);
302 /* PantherPoint PCH Power Management init */
303 static void ppt_pm_init(pci_dev_t dev)
305 debug("PantherPoint PM init\n");
306 x86_pci_write_config8(dev, 0xa9, 0x47);
307 setbits_le32(RCB_REG(0x2238), 1 << 0);
308 setbits_le32(RCB_REG(0x228c), 1 << 0);
309 setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14));
310 setbits_le16(RCB_REG(0x0900), 1 << 14);
311 writel(0xc03b8400, RCB_REG(0x2304));
312 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18));
313 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1));
314 clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf);
315 writel(0x054f0000, RCB_REG(0x3318));
316 writel(0x04000000, RCB_REG(0x3324));
317 setbits_le32(RCB_REG(0x3340), 0xfffff);
318 setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0));
319 writel(0x0001c000, RCB_REG(0x3360));
320 writel(0x00061100, RCB_REG(0x3368));
321 writel(0x7f8fdfff, RCB_REG(0x3378));
322 writel(0x000003fd, RCB_REG(0x337c));
323 writel(0x00001000, RCB_REG(0x3388));
324 writel(0x0001c000, RCB_REG(0x3390));
325 writel(0x00000800, RCB_REG(0x33a0));
326 writel(0x00001000, RCB_REG(0x33b0));
327 writel(0x00093900, RCB_REG(0x33c0));
328 writel(0x24653002, RCB_REG(0x33cc));
329 writel(0x067388fe, RCB_REG(0x33d0));
330 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060);
331 writel(0x01010000, RCB_REG(0x3a28));
332 writel(0x01010404, RCB_REG(0x3a2c));
333 writel(0x01040000, RCB_REG(0x3a80));
334 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001);
335 /* SATA 2/3 disabled */
336 setbits_le32(RCB_REG(0x3a84), 1 << 24);
337 /* SATA 4/5 disabled */
338 setbits_le32(RCB_REG(0x3a88), 1 << 0);
339 writel(0x00000001, RCB_REG(0x3a6c));
340 clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c);
341 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20);
342 setbits_le32(RCB_REG(0x33a4), (1 << 0));
343 writel(0, RCB_REG(0x33c8));
344 setbits_le32(RCB_REG(0x21b0), 0xf);
347 static void enable_hpet(void)
349 /* Move HPET to default address 0xfed00000 and enable it */
350 clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7);
353 static void enable_clock_gating(pci_dev_t dev)
358 setbits_le32(RCB_REG(0x2234), 0xf);
360 reg16 = x86_pci_read_config16(dev, GEN_PMCON_1);
361 reg16 |= (1 << 2) | (1 << 11);
362 x86_pci_write_config16(dev, GEN_PMCON_1, reg16);
364 pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
365 pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
366 pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
367 pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
369 reg32 = readl(RCB_REG(CG));
371 reg32 |= (1 << 29) | (1 << 28);
372 reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
382 writel(reg32, RCB_REG(CG));
384 setbits_le32(RCB_REG(0x38c0), 0x7);
385 setbits_le32(RCB_REG(0x36d4), 0x6680c004);
386 setbits_le32(RCB_REG(0x3564), 0x3);
389 #if CONFIG_HAVE_SMI_HANDLER
390 static void pch_lock_smm(pci_dev_t dev)
392 #if TEST_SMM_FLASH_LOCKDOWN
396 if (acpi_slp_type != 3) {
397 #if ENABLE_ACPI_MODE_IN_COREBOOT
398 debug("Enabling ACPI via APMC:\n");
399 outb(0xe1, 0xb2); /* Enable ACPI mode */
402 debug("Disabling ACPI via APMC:\n");
403 outb(0x1e, 0xb2); /* Disable ACPI mode */
408 /* Don't allow evil boot loaders, kernels, or
409 * userspace applications to deceive us:
413 #if TEST_SMM_FLASH_LOCKDOWN
415 debug("Locking BIOS to RO... ");
416 reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
417 debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
418 (reg8 & 1) ? "rw" : "ro");
419 reg8 &= ~(1 << 0); /* clear BIOSWE */
420 x86_pci_write_config8(dev, 0xdc, reg8);
421 reg8 |= (1 << 1); /* set BLE */
422 x86_pci_write_config8(dev, 0xdc, reg8);
424 reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
425 debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
426 (reg8 & 1) ? "rw" : "ro");
429 writeb(0, 0xfff00000);
431 reg8 |= (1 << 0); /* set BIOSWE */
432 x86_pci_write_config8(dev, 0xdc, reg8);
434 reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
435 debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
436 (reg8 & 1) ? "rw" : "ro");
442 static void pch_disable_smm_only_flashing(pci_dev_t dev)
446 debug("Enabling BIOS updates outside of SMM... ");
447 reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
449 x86_pci_write_config8(dev, 0xdc, reg8);
452 static void pch_fixups(pci_dev_t dev)
456 /* Indicate DRAM init done for MRC S3 to know it can resume */
457 gen_pmcon_2 = x86_pci_read_config8(dev, GEN_PMCON_2);
458 gen_pmcon_2 |= (1 << 7);
459 x86_pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
461 /* Enable DMI ASPM in the PCH */
462 clrbits_le32(RCB_REG(0x2304), 1 << 10);
463 setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10));
464 setbits_le32(RCB_REG(0x21a8), 0x3);
467 int lpc_early_init(const void *blob, int node, pci_dev_t dev)
476 count = fdtdec_get_int_array_count(blob, node, "intel,gen-dec",
477 (u32 *)values, sizeof(values) / sizeof(u32));
481 /* Set COM1/COM2 decode range */
482 x86_pci_write_config16(dev, LPC_IO_DEC, 0x0010);
484 /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
485 x86_pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
486 GAMEL_LPC_EN | COMA_LPC_EN);
488 /* Write all registers but use 0 if we run out of data */
489 count = count * sizeof(u32) / sizeof(values[0]);
490 for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
494 reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
495 x86_pci_write_config32(dev, LPC_GENX_DEC(i), reg);
501 int lpc_init(struct pci_controller *hose, pci_dev_t dev)
503 const void *blob = gd->fdt_blob;
506 debug("pch: lpc_init\n");
507 pci_write_bar32(hose, dev, 0, 0);
508 pci_write_bar32(hose, dev, 1, 0xff800000);
509 pci_write_bar32(hose, dev, 2, 0xfec00000);
510 pci_write_bar32(hose, dev, 3, 0x800);
511 pci_write_bar32(hose, dev, 4, 0x900);
513 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
517 /* Set the value for PCI command register. */
518 x86_pci_write_config16(dev, PCI_COMMAND, 0x000f);
520 /* IO APIC initialization. */
521 pch_enable_apic(dev);
523 pch_enable_serial_irqs(dev);
525 /* Setup the PIRQ. */
526 pch_pirq_init(blob, node, dev);
528 /* Setup power options. */
529 pch_power_options(blob, node, dev);
531 /* Initialize power management */
532 switch (pch_silicon_type()) {
533 case PCH_TYPE_CPT: /* CougarPoint */
536 case PCH_TYPE_PPT: /* PantherPoint */
540 printf("Unknown Chipset: %#02x.%dx\n", PCI_DEV(dev),
545 /* Initialize the real time clock. */
548 /* Initialize the High Precision Event Timers, if present. */
551 /* Initialize Clock Gating */
552 enable_clock_gating(dev);
554 pch_disable_smm_only_flashing(dev);
556 #if CONFIG_HAVE_SMI_HANDLER
565 void lpc_enable(pci_dev_t dev)
567 /* Enable PCH Display Port */
568 writew(0x0010, RCB_REG(DISPBDF));
569 setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);