2 * From Coreboot file of same name
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 The Chromium Authors
7 * SPDX-License-Identifier: GPL-2.0
15 #include <asm/lapic.h>
18 #include <asm/processor.h>
19 #include <asm/speedstep.h>
20 #include <asm/turbo.h>
21 #include <asm/arch/bd82x6x.h>
22 #include <asm/arch/model_206ax.h>
24 static void enable_vmx(void)
26 struct cpuid_result regs;
27 #ifdef CONFIG_ENABLE_VMX
35 /* Check that the VMX is supported before reading or writing the MSR. */
36 if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX)))
39 msr = msr_read(MSR_IA32_FEATURE_CONTROL);
41 if (msr.lo & (1 << 0)) {
42 debug("VMX is locked, so %s will do nothing\n", __func__);
43 /* VMX locked. If we set it again we get an illegal
49 /* The IA32_FEATURE_CONTROL MSR may initialize with random values.
50 * It must be cleared regardless of VMX config setting.
55 debug("%s VMX\n", enable ? "Enabling" : "Disabling");
58 * Even though the Intel manual says you must set the lock bit in
59 * addition to the VMX bit in order for VMX to work, it is incorrect.
60 * Thus we leave it unlocked for the OS to manage things itself.
61 * This is good for a few reasons:
62 * - No need to reflash the bios just to toggle the lock bit.
63 * - The VMX bits really really should match each other across cores,
64 * so hard locking it on one while another has the opposite setting
65 * can easily lead to crashes as code using VMX migrates between
67 * - Vendors that want to "upsell" from a bios that disables+locks to
68 * one that doesn't is sleazy.
69 * By leaving this to the OS (e.g. Linux), people can do exactly what
70 * they want on the fly, and do it correctly (e.g. across multiple
75 if (regs.ecx & CPUID_SMX)
79 msr_write(MSR_IA32_FEATURE_CONTROL, msr);
82 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
83 static const u8 power_limit_time_sec_to_msr[] = {
111 /* Convert POWER_LIMIT_1_TIME MSR value to seconds */
112 static const u8 power_limit_time_msr_to_sec[] = {
140 int cpu_config_tdp_levels(void)
142 struct cpuid_result result;
145 /* Minimum CPU revision */
147 if (result.eax < IVB_CONFIG_TDP_MIN_CPUID)
150 /* Bits 34:33 indicate how many levels supported */
151 platform_info = msr_read(MSR_PLATFORM_INFO);
152 return (platform_info.hi >> 1) & 3;
156 * Configure processor power limits if possible
157 * This must be done AFTER set of BIOS_RESET_CPL
159 void set_power_limits(u8 power_limit_1_time)
161 msr_t msr = msr_read(MSR_PLATFORM_INFO);
164 unsigned tdp, min_power, max_power, max_time;
165 u8 power_limit_1_val;
167 if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
170 if (!(msr.lo & PLATFORM_INFO_SET_TDP))
174 msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
175 power_unit = 2 << ((msr.lo & 0xf) - 1);
177 /* Get power defaults for this SKU */
178 msr = msr_read(MSR_PKG_POWER_SKU);
179 tdp = msr.lo & 0x7fff;
180 min_power = (msr.lo >> 16) & 0x7fff;
181 max_power = msr.hi & 0x7fff;
182 max_time = (msr.hi >> 16) & 0x7f;
184 debug("CPU TDP: %u Watts\n", tdp / power_unit);
186 if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
187 power_limit_1_time = power_limit_time_msr_to_sec[max_time];
189 if (min_power > 0 && tdp < min_power)
192 if (max_power > 0 && tdp > max_power)
195 power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
197 /* Set long term power limit to TDP */
199 limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
200 limit.lo |= PKG_POWER_LIMIT_EN;
201 limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
202 PKG_POWER_LIMIT_TIME_SHIFT;
204 /* Set short term power limit to 1.25 * TDP */
206 limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
207 limit.hi |= PKG_POWER_LIMIT_EN;
208 /* Power limit 2 time is only programmable on SNB EP/EX */
210 msr_write(MSR_PKG_POWER_LIMIT, limit);
212 /* Use nominal TDP values for CPUs with configurable TDP */
213 if (cpu_config_tdp_levels()) {
214 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
216 limit.lo = msr.lo & 0xff;
217 msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
221 static void configure_c_states(void)
223 struct cpuid_result result;
226 msr = msr_read(MSR_PMG_CST_CONFIG_CTL);
227 msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
228 msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
229 msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
230 msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
231 msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
232 msr.lo |= 7; /* No package C-state limit */
233 msr_write(MSR_PMG_CST_CONFIG_CTL, msr);
235 msr = msr_read(MSR_PMG_IO_CAPTURE_ADR);
237 msr.lo |= (PMB0_BASE + 4); /* LVL_2 base address */
238 msr.lo |= (2 << 16); /* CST Range: C7 is max C-state */
239 msr_write(MSR_PMG_IO_CAPTURE_ADR, msr);
241 msr = msr_read(MSR_MISC_PWR_MGMT);
242 msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
243 msr_write(MSR_MISC_PWR_MGMT, msr);
245 msr = msr_read(MSR_POWER_CTL);
246 msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
247 msr.lo |= (1 << 1); /* C1E Enable */
248 msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
249 msr_write(MSR_POWER_CTL, msr);
251 /* C3 Interrupt Response Time Limit */
253 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
254 msr_write(MSR_PKGC3_IRTL, msr);
256 /* C6 Interrupt Response Time Limit */
258 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
259 msr_write(MSR_PKGC6_IRTL, msr);
261 /* C7 Interrupt Response Time Limit */
263 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
264 msr_write(MSR_PKGC7_IRTL, msr);
266 /* Primary Plane Current Limit */
267 msr = msr_read(MSR_PP0_CURRENT_CONFIG);
269 msr.lo |= PP0_CURRENT_LIMIT;
270 msr_write(MSR_PP0_CURRENT_CONFIG, msr);
272 /* Secondary Plane Current Limit */
273 msr = msr_read(MSR_PP1_CURRENT_CONFIG);
276 if (result.eax >= 0x30600)
277 msr.lo |= PP1_CURRENT_LIMIT_IVB;
279 msr.lo |= PP1_CURRENT_LIMIT_SNB;
280 msr_write(MSR_PP1_CURRENT_CONFIG, msr);
283 static int configure_thermal_target(void)
289 /* Find pointer to CPU configuration */
290 node = fdtdec_next_compatible(gd->fdt_blob, 0,
291 COMPAT_INTEL_MODEL_206AX);
294 tcc_offset = fdtdec_get_int(gd->fdt_blob, node, "tcc-offset", 0);
296 /* Set TCC activaiton offset if supported */
297 msr = msr_read(MSR_PLATFORM_INFO);
298 if ((msr.lo & (1 << 30)) && tcc_offset) {
299 msr = msr_read(MSR_TEMPERATURE_TARGET);
300 msr.lo &= ~(0xf << 24); /* Bits 27:24 */
301 msr.lo |= (tcc_offset & 0xf) << 24;
302 msr_write(MSR_TEMPERATURE_TARGET, msr);
308 static void configure_misc(void)
312 msr = msr_read(IA32_MISC_ENABLE);
313 msr.lo |= (1 << 0); /* Fast String enable */
314 msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
315 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
316 msr_write(IA32_MISC_ENABLE, msr);
318 /* Disable Thermal interrupts */
321 msr_write(IA32_THERM_INTERRUPT, msr);
323 /* Enable package critical interrupt only */
326 msr_write(IA32_PACKAGE_THERM_INTERRUPT, msr);
329 static void enable_lapic_tpr(void)
333 msr = msr_read(MSR_PIC_MSG_CONTROL);
334 msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
335 msr_write(MSR_PIC_MSG_CONTROL, msr);
338 static void configure_dca_cap(void)
340 struct cpuid_result cpuid_regs;
343 /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
344 cpuid_regs = cpuid(1);
345 if (cpuid_regs.ecx & (1 << 18)) {
346 msr = msr_read(IA32_PLATFORM_DCA_CAP);
348 msr_write(IA32_PLATFORM_DCA_CAP, msr);
352 static void set_max_ratio(void)
358 /* Check for configurable TDP option */
359 if (cpu_config_tdp_levels()) {
360 /* Set to nominal TDP ratio */
361 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
362 perf_ctl.lo = (msr.lo & 0xff) << 8;
364 /* Platform Info bits 15:8 give max ratio */
365 msr = msr_read(MSR_PLATFORM_INFO);
366 perf_ctl.lo = msr.lo & 0xff00;
368 msr_write(IA32_PERF_CTL, perf_ctl);
370 debug("model_x06ax: frequency set to %d\n",
371 ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
374 static void set_energy_perf_bias(u8 policy)
378 /* Energy Policy is bits 3:0 */
379 msr = msr_read(IA32_ENERGY_PERFORMANCE_BIAS);
381 msr.lo |= policy & 0xf;
382 msr_write(IA32_ENERGY_PERFORMANCE_BIAS, msr);
384 debug("model_x06ax: energy policy set to %u\n", policy);
387 static void configure_mca(void)
394 /* This should only be done on a cold boot */
395 for (i = 0; i < 7; i++)
396 msr_write(IA32_MC0_STATUS + (i * 4), msr);
400 static unsigned ehci_debug_addr;
404 * Initialize any extra cores/threads in this package.
406 static int intel_cores_init(struct x86_cpu_priv *cpu)
408 struct cpuid_result result;
409 unsigned threads_per_package, threads_per_core, i;
411 /* Logical processors (threads) per core */
412 result = cpuid_ext(0xb, 0);
413 threads_per_core = result.ebx & 0xffff;
415 /* Logical processors (threads) per package */
416 result = cpuid_ext(0xb, 1);
417 threads_per_package = result.ebx & 0xffff;
419 debug("CPU: %u has %u cores, %u threads per core\n",
420 cpu->apic_id, threads_per_package / threads_per_core,
423 for (i = 1; i < threads_per_package; ++i) {
424 struct x86_cpu_priv *new_cpu;
426 new_cpu = calloc(1, sizeof(*new_cpu));
430 new_cpu->apic_id = cpu->apic_id + i;
432 /* Update APIC ID if no hyperthreading */
433 if (threads_per_core == 1)
434 new_cpu->apic_id <<= 1;
436 debug("CPU: %u has core %u\n", cpu->apic_id, new_cpu->apic_id);
438 #if 0 && CONFIG_SMP && CONFIG_MAX_CPUS > 1
439 /* TODO(sjg@chromium.org): Start the new cpu */
440 if (!start_cpu(new_cpu)) {
441 /* Record the error in cpu? */
442 printk(BIOS_ERR, "CPU %u would not start!\n",
444 new_cpu->start_err = 1;
452 int model_206ax_init(struct x86_cpu_priv *cpu)
456 /* Clear out pending MCEs */
460 /* Is this caution really needed? */
461 if (!ehci_debug_addr)
462 ehci_debug_addr = get_ehci_debug();
466 /* Setup MTRRs based on physical address size */
467 #if 0 /* TODO: Implement this */
468 struct cpuid_result cpuid_regs;
470 cpuid_regs = cpuid(0x80000008);
471 x86_setup_fixed_mtrrs();
472 x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2);
477 set_ehci_debug(ehci_debug_addr);
480 /* Enable the local cpu apics */
484 /* Enable virtualization if enabled in CMOS */
487 /* Configure C States */
488 configure_c_states();
490 /* Configure Enhanced SpeedStep and Thermal Sensors */
493 /* Thermal throttle activation offset */
494 ret = configure_thermal_target();
498 /* Enable Direct Cache Access */
501 /* Set energy policy */
502 set_energy_perf_bias(ENERGY_POLICY_NORMAL);
510 /* Start up extra cores */
511 intel_cores_init(cpu);