2 * From Coreboot file of same name
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 The Chromium Authors
7 * SPDX-License-Identifier: GPL-2.0
17 #include <asm/cpu_x86.h>
18 #include <asm/lapic.h>
20 #include <asm/msr-index.h>
22 #include <asm/processor.h>
23 #include <asm/speedstep.h>
24 #include <asm/turbo.h>
25 #include <asm/arch/bd82x6x.h>
26 #include <asm/arch/model_206ax.h>
28 static void enable_vmx(void)
30 struct cpuid_result regs;
31 #ifdef CONFIG_ENABLE_VMX
39 /* Check that the VMX is supported before reading or writing the MSR. */
40 if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX)))
43 msr = msr_read(MSR_IA32_FEATURE_CONTROL);
45 if (msr.lo & (1 << 0)) {
46 debug("VMX is locked, so %s will do nothing\n", __func__);
47 /* VMX locked. If we set it again we get an illegal
53 /* The IA32_FEATURE_CONTROL MSR may initialize with random values.
54 * It must be cleared regardless of VMX config setting.
59 debug("%s VMX\n", enable ? "Enabling" : "Disabling");
62 * Even though the Intel manual says you must set the lock bit in
63 * addition to the VMX bit in order for VMX to work, it is incorrect.
64 * Thus we leave it unlocked for the OS to manage things itself.
65 * This is good for a few reasons:
66 * - No need to reflash the bios just to toggle the lock bit.
67 * - The VMX bits really really should match each other across cores,
68 * so hard locking it on one while another has the opposite setting
69 * can easily lead to crashes as code using VMX migrates between
71 * - Vendors that want to "upsell" from a bios that disables+locks to
72 * one that doesn't is sleazy.
73 * By leaving this to the OS (e.g. Linux), people can do exactly what
74 * they want on the fly, and do it correctly (e.g. across multiple
79 if (regs.ecx & CPUID_SMX)
83 msr_write(MSR_IA32_FEATURE_CONTROL, msr);
86 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
87 static const u8 power_limit_time_sec_to_msr[] = {
115 /* Convert POWER_LIMIT_1_TIME MSR value to seconds */
116 static const u8 power_limit_time_msr_to_sec[] = {
144 int cpu_config_tdp_levels(void)
146 struct cpuid_result result;
149 /* Minimum CPU revision */
151 if (result.eax < IVB_CONFIG_TDP_MIN_CPUID)
154 /* Bits 34:33 indicate how many levels supported */
155 platform_info = msr_read(MSR_PLATFORM_INFO);
156 return (platform_info.hi >> 1) & 3;
160 * Configure processor power limits if possible
161 * This must be done AFTER set of BIOS_RESET_CPL
163 void set_power_limits(u8 power_limit_1_time)
165 msr_t msr = msr_read(MSR_PLATFORM_INFO);
168 unsigned tdp, min_power, max_power, max_time;
169 u8 power_limit_1_val;
171 if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
174 if (!(msr.lo & PLATFORM_INFO_SET_TDP))
178 msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
179 power_unit = 2 << ((msr.lo & 0xf) - 1);
181 /* Get power defaults for this SKU */
182 msr = msr_read(MSR_PKG_POWER_SKU);
183 tdp = msr.lo & 0x7fff;
184 min_power = (msr.lo >> 16) & 0x7fff;
185 max_power = msr.hi & 0x7fff;
186 max_time = (msr.hi >> 16) & 0x7f;
188 debug("CPU TDP: %u Watts\n", tdp / power_unit);
190 if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
191 power_limit_1_time = power_limit_time_msr_to_sec[max_time];
193 if (min_power > 0 && tdp < min_power)
196 if (max_power > 0 && tdp > max_power)
199 power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
201 /* Set long term power limit to TDP */
203 limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
204 limit.lo |= PKG_POWER_LIMIT_EN;
205 limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
206 PKG_POWER_LIMIT_TIME_SHIFT;
208 /* Set short term power limit to 1.25 * TDP */
210 limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
211 limit.hi |= PKG_POWER_LIMIT_EN;
212 /* Power limit 2 time is only programmable on SNB EP/EX */
214 msr_write(MSR_PKG_POWER_LIMIT, limit);
216 /* Use nominal TDP values for CPUs with configurable TDP */
217 if (cpu_config_tdp_levels()) {
218 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
220 limit.lo = msr.lo & 0xff;
221 msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
225 static void configure_c_states(void)
227 struct cpuid_result result;
230 msr = msr_read(MSR_PMG_CST_CONFIG_CTL);
231 msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
232 msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
233 msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
234 msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
235 msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
236 msr.lo |= 7; /* No package C-state limit */
237 msr_write(MSR_PMG_CST_CONFIG_CTL, msr);
239 msr = msr_read(MSR_PMG_IO_CAPTURE_ADR);
241 msr.lo |= (PMB0_BASE + 4); /* LVL_2 base address */
242 msr.lo |= (2 << 16); /* CST Range: C7 is max C-state */
243 msr_write(MSR_PMG_IO_CAPTURE_ADR, msr);
245 msr = msr_read(MSR_MISC_PWR_MGMT);
246 msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
247 msr_write(MSR_MISC_PWR_MGMT, msr);
249 msr = msr_read(MSR_POWER_CTL);
250 msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
251 msr.lo |= (1 << 1); /* C1E Enable */
252 msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
253 msr_write(MSR_POWER_CTL, msr);
255 /* C3 Interrupt Response Time Limit */
257 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
258 msr_write(MSR_PKGC3_IRTL, msr);
260 /* C6 Interrupt Response Time Limit */
262 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
263 msr_write(MSR_PKGC6_IRTL, msr);
265 /* C7 Interrupt Response Time Limit */
267 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
268 msr_write(MSR_PKGC7_IRTL, msr);
270 /* Primary Plane Current Limit */
271 msr = msr_read(MSR_PP0_CURRENT_CONFIG);
273 msr.lo |= PP0_CURRENT_LIMIT;
274 msr_write(MSR_PP0_CURRENT_CONFIG, msr);
276 /* Secondary Plane Current Limit */
277 msr = msr_read(MSR_PP1_CURRENT_CONFIG);
280 if (result.eax >= 0x30600)
281 msr.lo |= PP1_CURRENT_LIMIT_IVB;
283 msr.lo |= PP1_CURRENT_LIMIT_SNB;
284 msr_write(MSR_PP1_CURRENT_CONFIG, msr);
287 static int configure_thermal_target(struct udevice *dev)
292 tcc_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "tcc-offset",
295 /* Set TCC activaiton offset if supported */
296 msr = msr_read(MSR_PLATFORM_INFO);
297 if ((msr.lo & (1 << 30)) && tcc_offset) {
298 msr = msr_read(MSR_TEMPERATURE_TARGET);
299 msr.lo &= ~(0xf << 24); /* Bits 27:24 */
300 msr.lo |= (tcc_offset & 0xf) << 24;
301 msr_write(MSR_TEMPERATURE_TARGET, msr);
307 static void configure_misc(void)
311 msr = msr_read(IA32_MISC_ENABLE);
312 msr.lo |= (1 << 0); /* Fast String enable */
313 msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
314 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
315 msr_write(IA32_MISC_ENABLE, msr);
317 /* Disable Thermal interrupts */
320 msr_write(IA32_THERM_INTERRUPT, msr);
322 /* Enable package critical interrupt only */
325 msr_write(IA32_PACKAGE_THERM_INTERRUPT, msr);
328 static void enable_lapic_tpr(void)
332 msr = msr_read(MSR_PIC_MSG_CONTROL);
333 msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
334 msr_write(MSR_PIC_MSG_CONTROL, msr);
337 static void configure_dca_cap(void)
339 struct cpuid_result cpuid_regs;
342 /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
343 cpuid_regs = cpuid(1);
344 if (cpuid_regs.ecx & (1 << 18)) {
345 msr = msr_read(IA32_PLATFORM_DCA_CAP);
347 msr_write(IA32_PLATFORM_DCA_CAP, msr);
351 static void set_max_ratio(void)
357 /* Check for configurable TDP option */
358 if (cpu_config_tdp_levels()) {
359 /* Set to nominal TDP ratio */
360 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
361 perf_ctl.lo = (msr.lo & 0xff) << 8;
363 /* Platform Info bits 15:8 give max ratio */
364 msr = msr_read(MSR_PLATFORM_INFO);
365 perf_ctl.lo = msr.lo & 0xff00;
367 msr_write(MSR_IA32_PERF_CTL, perf_ctl);
369 debug("model_x06ax: frequency set to %d\n",
370 ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
373 static void set_energy_perf_bias(u8 policy)
377 /* Energy Policy is bits 3:0 */
378 msr = msr_read(IA32_ENERGY_PERFORMANCE_BIAS);
380 msr.lo |= policy & 0xf;
381 msr_write(IA32_ENERGY_PERFORMANCE_BIAS, msr);
383 debug("model_x06ax: energy policy set to %u\n", policy);
386 static void configure_mca(void)
393 /* This should only be done on a cold boot */
394 for (i = 0; i < 7; i++)
395 msr_write(IA32_MC0_STATUS + (i * 4), msr);
399 static unsigned ehci_debug_addr;
402 static int model_206ax_init(struct udevice *dev)
406 /* Clear out pending MCEs */
410 /* Is this caution really needed? */
411 if (!ehci_debug_addr)
412 ehci_debug_addr = get_ehci_debug();
417 set_ehci_debug(ehci_debug_addr);
420 /* Enable the local cpu apics */
424 /* Enable virtualization if enabled in CMOS */
427 /* Configure C States */
428 configure_c_states();
430 /* Configure Enhanced SpeedStep and Thermal Sensors */
433 /* Thermal throttle activation offset */
434 ret = configure_thermal_target(dev);
436 debug("Cannot set thermal target\n");
440 /* Enable Direct Cache Access */
443 /* Set energy policy */
444 set_energy_perf_bias(ENERGY_POLICY_NORMAL);
455 static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info)
459 msr = msr_read(MSR_IA32_PERF_CTL);
460 info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 1000000;
461 info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
467 static int model_206ax_get_count(struct udevice *dev)
472 static int cpu_x86_model_206ax_probe(struct udevice *dev)
475 model_206ax_init(dev);
480 static const struct cpu_ops cpu_x86_model_206ax_ops = {
481 .get_desc = cpu_x86_get_desc,
482 .get_info = model_206ax_get_info,
483 .get_count = model_206ax_get_count,
486 static const struct udevice_id cpu_x86_model_206ax_ids[] = {
487 { .compatible = "intel,core-gen3" },
491 U_BOOT_DRIVER(cpu_x86_model_206ax_drv) = {
492 .name = "cpu_x86_model_206ax",
494 .of_match = cpu_x86_model_206ax_ids,
495 .bind = cpu_x86_bind,
496 .probe = cpu_x86_model_206ax_probe,
497 .ops = &cpu_x86_model_206ax_ops,