2 * From Coreboot file of same name
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 The Chromium Authors
7 * SPDX-License-Identifier: GPL-2.0
16 #include <asm/cpu_x86.h>
18 #include <asm/msr-index.h>
20 #include <asm/processor.h>
21 #include <asm/speedstep.h>
22 #include <asm/turbo.h>
23 #include <asm/arch/bd82x6x.h>
24 #include <asm/arch/model_206ax.h>
26 static void enable_vmx(void)
28 struct cpuid_result regs;
29 #ifdef CONFIG_ENABLE_VMX
37 /* Check that the VMX is supported before reading or writing the MSR. */
38 if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX)))
41 msr = msr_read(MSR_IA32_FEATURE_CONTROL);
43 if (msr.lo & (1 << 0)) {
44 debug("VMX is locked, so %s will do nothing\n", __func__);
45 /* VMX locked. If we set it again we get an illegal
51 /* The IA32_FEATURE_CONTROL MSR may initialize with random values.
52 * It must be cleared regardless of VMX config setting.
57 debug("%s VMX\n", enable ? "Enabling" : "Disabling");
60 * Even though the Intel manual says you must set the lock bit in
61 * addition to the VMX bit in order for VMX to work, it is incorrect.
62 * Thus we leave it unlocked for the OS to manage things itself.
63 * This is good for a few reasons:
64 * - No need to reflash the bios just to toggle the lock bit.
65 * - The VMX bits really really should match each other across cores,
66 * so hard locking it on one while another has the opposite setting
67 * can easily lead to crashes as code using VMX migrates between
69 * - Vendors that want to "upsell" from a bios that disables+locks to
70 * one that doesn't is sleazy.
71 * By leaving this to the OS (e.g. Linux), people can do exactly what
72 * they want on the fly, and do it correctly (e.g. across multiple
77 if (regs.ecx & CPUID_SMX)
81 msr_write(MSR_IA32_FEATURE_CONTROL, msr);
84 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
85 static const u8 power_limit_time_sec_to_msr[] = {
113 /* Convert POWER_LIMIT_1_TIME MSR value to seconds */
114 static const u8 power_limit_time_msr_to_sec[] = {
142 int cpu_config_tdp_levels(void)
144 struct cpuid_result result;
147 /* Minimum CPU revision */
149 if (result.eax < IVB_CONFIG_TDP_MIN_CPUID)
152 /* Bits 34:33 indicate how many levels supported */
153 platform_info = msr_read(MSR_PLATFORM_INFO);
154 return (platform_info.hi >> 1) & 3;
158 * Configure processor power limits if possible
159 * This must be done AFTER set of BIOS_RESET_CPL
161 void set_power_limits(u8 power_limit_1_time)
163 msr_t msr = msr_read(MSR_PLATFORM_INFO);
166 unsigned tdp, min_power, max_power, max_time;
167 u8 power_limit_1_val;
169 if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
172 if (!(msr.lo & PLATFORM_INFO_SET_TDP))
176 msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
177 power_unit = 2 << ((msr.lo & 0xf) - 1);
179 /* Get power defaults for this SKU */
180 msr = msr_read(MSR_PKG_POWER_SKU);
181 tdp = msr.lo & 0x7fff;
182 min_power = (msr.lo >> 16) & 0x7fff;
183 max_power = msr.hi & 0x7fff;
184 max_time = (msr.hi >> 16) & 0x7f;
186 debug("CPU TDP: %u Watts\n", tdp / power_unit);
188 if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
189 power_limit_1_time = power_limit_time_msr_to_sec[max_time];
191 if (min_power > 0 && tdp < min_power)
194 if (max_power > 0 && tdp > max_power)
197 power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
199 /* Set long term power limit to TDP */
201 limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
202 limit.lo |= PKG_POWER_LIMIT_EN;
203 limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
204 PKG_POWER_LIMIT_TIME_SHIFT;
206 /* Set short term power limit to 1.25 * TDP */
208 limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
209 limit.hi |= PKG_POWER_LIMIT_EN;
210 /* Power limit 2 time is only programmable on SNB EP/EX */
212 msr_write(MSR_PKG_POWER_LIMIT, limit);
214 /* Use nominal TDP values for CPUs with configurable TDP */
215 if (cpu_config_tdp_levels()) {
216 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
218 limit.lo = msr.lo & 0xff;
219 msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
223 static void configure_c_states(void)
225 struct cpuid_result result;
228 msr = msr_read(MSR_PMG_CST_CONFIG_CTL);
229 msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
230 msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
231 msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
232 msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
233 msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
234 msr.lo |= 7; /* No package C-state limit */
235 msr_write(MSR_PMG_CST_CONFIG_CTL, msr);
237 msr = msr_read(MSR_PMG_IO_CAPTURE_ADR);
239 msr.lo |= (PMB0_BASE + 4); /* LVL_2 base address */
240 msr.lo |= (2 << 16); /* CST Range: C7 is max C-state */
241 msr_write(MSR_PMG_IO_CAPTURE_ADR, msr);
243 msr = msr_read(MSR_MISC_PWR_MGMT);
244 msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
245 msr_write(MSR_MISC_PWR_MGMT, msr);
247 msr = msr_read(MSR_POWER_CTL);
248 msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
249 msr.lo |= (1 << 1); /* C1E Enable */
250 msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
251 msr_write(MSR_POWER_CTL, msr);
253 /* C3 Interrupt Response Time Limit */
255 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
256 msr_write(MSR_PKGC3_IRTL, msr);
258 /* C6 Interrupt Response Time Limit */
260 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
261 msr_write(MSR_PKGC6_IRTL, msr);
263 /* C7 Interrupt Response Time Limit */
265 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
266 msr_write(MSR_PKGC7_IRTL, msr);
268 /* Primary Plane Current Limit */
269 msr = msr_read(MSR_PP0_CURRENT_CONFIG);
271 msr.lo |= PP0_CURRENT_LIMIT;
272 msr_write(MSR_PP0_CURRENT_CONFIG, msr);
274 /* Secondary Plane Current Limit */
275 msr = msr_read(MSR_PP1_CURRENT_CONFIG);
278 if (result.eax >= 0x30600)
279 msr.lo |= PP1_CURRENT_LIMIT_IVB;
281 msr.lo |= PP1_CURRENT_LIMIT_SNB;
282 msr_write(MSR_PP1_CURRENT_CONFIG, msr);
285 static int configure_thermal_target(struct udevice *dev)
290 tcc_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "tcc-offset",
293 /* Set TCC activaiton offset if supported */
294 msr = msr_read(MSR_PLATFORM_INFO);
295 if ((msr.lo & (1 << 30)) && tcc_offset) {
296 msr = msr_read(MSR_TEMPERATURE_TARGET);
297 msr.lo &= ~(0xf << 24); /* Bits 27:24 */
298 msr.lo |= (tcc_offset & 0xf) << 24;
299 msr_write(MSR_TEMPERATURE_TARGET, msr);
305 static void configure_misc(void)
309 msr = msr_read(IA32_MISC_ENABLE);
310 msr.lo |= (1 << 0); /* Fast String enable */
311 msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
312 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
313 msr_write(IA32_MISC_ENABLE, msr);
315 /* Disable Thermal interrupts */
318 msr_write(IA32_THERM_INTERRUPT, msr);
320 /* Enable package critical interrupt only */
323 msr_write(IA32_PACKAGE_THERM_INTERRUPT, msr);
326 static void enable_lapic_tpr(void)
330 msr = msr_read(MSR_PIC_MSG_CONTROL);
331 msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
332 msr_write(MSR_PIC_MSG_CONTROL, msr);
335 static void configure_dca_cap(void)
337 struct cpuid_result cpuid_regs;
340 /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
341 cpuid_regs = cpuid(1);
342 if (cpuid_regs.ecx & (1 << 18)) {
343 msr = msr_read(IA32_PLATFORM_DCA_CAP);
345 msr_write(IA32_PLATFORM_DCA_CAP, msr);
349 static void set_max_ratio(void)
355 /* Check for configurable TDP option */
356 if (cpu_config_tdp_levels()) {
357 /* Set to nominal TDP ratio */
358 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
359 perf_ctl.lo = (msr.lo & 0xff) << 8;
361 /* Platform Info bits 15:8 give max ratio */
362 msr = msr_read(MSR_PLATFORM_INFO);
363 perf_ctl.lo = msr.lo & 0xff00;
365 msr_write(MSR_IA32_PERF_CTL, perf_ctl);
367 debug("model_x06ax: frequency set to %d\n",
368 ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
371 static void set_energy_perf_bias(u8 policy)
375 /* Energy Policy is bits 3:0 */
376 msr = msr_read(IA32_ENERGY_PERFORMANCE_BIAS);
378 msr.lo |= policy & 0xf;
379 msr_write(IA32_ENERGY_PERFORMANCE_BIAS, msr);
381 debug("model_x06ax: energy policy set to %u\n", policy);
384 static void configure_mca(void)
391 /* This should only be done on a cold boot */
392 for (i = 0; i < 7; i++)
393 msr_write(IA32_MC0_STATUS + (i * 4), msr);
397 static unsigned ehci_debug_addr;
400 static int model_206ax_init(struct udevice *dev)
404 /* Clear out pending MCEs */
408 /* Is this caution really needed? */
409 if (!ehci_debug_addr)
410 ehci_debug_addr = get_ehci_debug();
415 set_ehci_debug(ehci_debug_addr);
418 /* Enable the local cpu apics */
421 /* Enable virtualization if enabled in CMOS */
424 /* Configure C States */
425 configure_c_states();
427 /* Configure Enhanced SpeedStep and Thermal Sensors */
430 /* Thermal throttle activation offset */
431 ret = configure_thermal_target(dev);
433 debug("Cannot set thermal target\n");
437 /* Enable Direct Cache Access */
440 /* Set energy policy */
441 set_energy_perf_bias(ENERGY_POLICY_NORMAL);
452 static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info)
456 msr = msr_read(MSR_IA32_PERF_CTL);
457 info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 1000000;
458 info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
464 static int model_206ax_get_count(struct udevice *dev)
469 static int cpu_x86_model_206ax_probe(struct udevice *dev)
472 model_206ax_init(dev);
477 static const struct cpu_ops cpu_x86_model_206ax_ops = {
478 .get_desc = cpu_x86_get_desc,
479 .get_info = model_206ax_get_info,
480 .get_count = model_206ax_get_count,
483 static const struct udevice_id cpu_x86_model_206ax_ids[] = {
484 { .compatible = "intel,core-gen3" },
488 U_BOOT_DRIVER(cpu_x86_model_206ax_drv) = {
489 .name = "cpu_x86_model_206ax",
491 .of_match = cpu_x86_model_206ax_ids,
492 .bind = cpu_x86_bind,
493 .probe = cpu_x86_model_206ax_probe,
494 .ops = &cpu_x86_model_206ax_ops,