2 * From Coreboot northbridge/intel/sandybridge/northbridge.c
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 The Chromium Authors
7 * SPDX-License-Identifier: GPL-2.0
17 #include <asm/processor.h>
18 #include <asm/arch/pch.h>
19 #include <asm/arch/model_206ax.h>
20 #include <asm/arch/sandybridge.h>
22 static int bridge_revision_id = -1;
24 int bridge_silicon_revision(void)
26 if (bridge_revision_id < 0) {
27 struct cpuid_result result;
28 uint8_t stepping, bridge_id;
32 stepping = result.eax & 0xf;
33 dev = PCI_BDF(0, 0, 0);
34 bridge_id = x86_pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0;
35 bridge_revision_id = bridge_id | stepping;
38 return bridge_revision_id;
42 * Reserve everything between A segment and 1MB:
44 * 0xa0000 - 0xbffff: legacy VGA
45 * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
46 * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
48 static const int legacy_hole_base_k = 0xa0000 / 1024;
49 static const int legacy_hole_size_k = 384;
51 static int get_pcie_bar(u32 *base, u32 *len)
53 pci_dev_t dev = PCI_BDF(0, 0, 0);
59 pciexbar_reg = x86_pci_read_config32(dev, PCIEXBAR);
61 if (!(pciexbar_reg & (1 << 0)))
64 switch ((pciexbar_reg >> 1) & 3) {
66 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
68 *len = 256 * 1024 * 1024;
71 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
72 (1 << 28) | (1 << 27));
73 *len = 128 * 1024 * 1024;
76 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
77 (1 << 28) | (1 << 27) | (1 << 26));
78 *len = 64 * 1024 * 1024;
85 static void add_fixed_resources(pci_dev_t dev, int index)
87 u32 pcie_config_base, pcie_config_size;
89 if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
90 debug("Adding PCIe config bar base=0x%08x size=0x%x\n",
91 pcie_config_base, pcie_config_size);
95 static void northbridge_dmi_init(pci_dev_t dev)
97 /* Clear error status bits */
98 writel(0xffffffff, DMIBAR_REG(0x1c4));
99 writel(0xffffffff, DMIBAR_REG(0x1d0));
101 /* Steps prior to DMI ASPM */
102 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
103 clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20),
107 setbits_le32(DMIBAR_REG(0x238), 1 << 29);
109 if (bridge_silicon_revision() >= SNB_STEP_D0) {
110 setbits_le32(DMIBAR_REG(0x1f8), 1 << 16);
111 } else if (bridge_silicon_revision() >= SNB_STEP_D1) {
112 clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16);
113 setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23));
116 /* Enable ASPM on SNB link, should happen before PCH link */
117 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB)
118 setbits_le32(DMIBAR_REG(0xd04), 1 << 4);
120 setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0));
123 void northbridge_init(pci_dev_t dev)
127 add_fixed_resources(dev, 6);
128 northbridge_dmi_init(dev);
130 bridge_type = readl(MCHBAR_REG(0x5f10));
131 bridge_type &= ~0xff;
133 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
134 /* Enable Power Aware Interrupt Routing - fixed priority */
135 clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4);
137 /* 30h for IvyBridge */
140 /* 20h for Sandybridge */
143 writel(bridge_type, MCHBAR_REG(0x5f10));
146 * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
147 * that BIOS has initialized memory and power management
149 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1);
150 debug("Set BIOS_RESET_CPL\n");
152 /* Configure turbo power limits 1ms after reset complete bit */
154 set_power_limits(28);
157 * CPUs with configurable TDP also need power limits set
158 * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT.
160 if (cpu_config_tdp_levels()) {
161 msr_t msr = msr_read(MSR_PKG_POWER_LIMIT);
163 writel(msr.lo, MCHBAR_REG(0x59A0));
164 writel(msr.hi, MCHBAR_REG(0x59A4));
167 /* Set here before graphics PM init */
168 writel(0x00100001, MCHBAR_REG(0x5500));
171 void northbridge_enable(pci_dev_t dev)
175 static void sandybridge_setup_northbridge_bars(struct udevice *dev)
177 /* Set up all hardcoded northbridge BARs */
178 debug("Setting up static registers\n");
179 dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1);
180 dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
181 dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1);
182 dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32);
183 /* 64MB - busses 0-63 */
184 dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
185 dm_pci_write_config32(dev, PCIEXBAR + 4,
186 (0LL + DEFAULT_PCIEXBAR) >> 32);
187 dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1);
188 dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
190 /* Set C0000-FFFFF to access RAM on both reads and writes */
191 dm_pci_write_config8(dev, PAM0, 0x30);
192 dm_pci_write_config8(dev, PAM1, 0x33);
193 dm_pci_write_config8(dev, PAM2, 0x33);
194 dm_pci_write_config8(dev, PAM3, 0x33);
195 dm_pci_write_config8(dev, PAM4, 0x33);
196 dm_pci_write_config8(dev, PAM5, 0x33);
197 dm_pci_write_config8(dev, PAM6, 0x33);
200 static int bd82x6x_northbridge_early_init(struct udevice *dev)
202 const int chipset_type = SANDYBRIDGE_MOBILE;
206 /* Device ID Override Enable should be done very early */
207 dm_pci_read_config32(dev, 0xe4, &capid0_a);
208 if (capid0_a & (1 << 10)) {
209 dm_pci_read_config8(dev, 0xf3, ®8);
210 reg8 &= ~7; /* Clear 2:0 */
212 if (chipset_type == SANDYBRIDGE_MOBILE)
213 reg8 |= 1; /* Set bit 0 */
215 dm_pci_write_config8(dev, 0xf3, reg8);
218 sandybridge_setup_northbridge_bars(dev);
221 dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
226 static int bd82x6x_northbridge_probe(struct udevice *dev)
228 if (!(gd->flags & GD_FLG_RELOC))
229 return bd82x6x_northbridge_early_init(dev);
231 northbridge_enable(PCH_DEV);
232 northbridge_init(PCH_DEV);
237 static const struct udevice_id bd82x6x_northbridge_ids[] = {
238 { .compatible = "intel,bd82x6x-northbridge" },
242 U_BOOT_DRIVER(bd82x6x_northbridge_drv) = {
243 .name = "bd82x6x_northbridge",
244 .id = UCLASS_NORTHBRIDGE,
245 .of_match = bd82x6x_northbridge_ids,
246 .probe = bd82x6x_northbridge_probe,