2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2008,2009
4 * Graeme Russ, <graeme.russ@gmail.com>
7 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/bd82x6x.h>
16 #include <asm/arch/pch.h>
18 static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
19 struct pci_config_table *table)
23 hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
25 pci_hose_scan_bus(hose, secondary);
28 static struct pci_config_table pci_ivybridge_config_table[] = {
29 /* vendor, device, class, bus, dev, func */
30 { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
31 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
35 void board_pci_setup_hose(struct pci_controller *hose)
37 hose->config_table = pci_ivybridge_config_table;
38 hose->first_busno = 0;
41 /* PCI memory space */
42 pci_set_region(hose->regions + 0,
49 pci_set_region(hose->regions + 1,
55 pci_set_region(hose->regions + 2,
61 hose->region_count = 3;
64 int board_pci_pre_scan(struct pci_controller *hose)
73 reg16 = pci_read_config16(dev, PCI_COMMAND);
74 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
75 pci_write_config16(dev, PCI_COMMAND, reg16);
78 * Clear non-reserved bits in status register.
80 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
81 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
82 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
84 pci_write_bar32(hose, dev, 0, 0xf0000000);
89 int board_pci_post_scan(struct pci_controller *hose)
93 ret = bd82x6x_init_pci_devices();
95 printf("bd82x6x_init_pci_devices() failed: %d\n", ret);