2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2008,2009
4 * Graeme Russ, <graeme.russ@gmail.com>
7 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
9 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/bd82x6x.h>
18 #include <asm/arch/pch.h>
20 static int pci_ivybridge_probe(struct udevice *bus)
22 struct pci_controller *hose = dev_get_uclass_priv(bus);
26 if (!(gd->flags & GD_FLG_RELOC))
34 reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
35 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
36 x86_pci_write_config16(dev, PCI_COMMAND, reg16);
39 * Clear non-reserved bits in status register.
41 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
42 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
43 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
45 pci_write_bar32(hose, dev, 0, 0xf0000000);
51 static const struct dm_pci_ops pci_ivybridge_ops = {
52 .read_config = pci_x86_read_config,
53 .write_config = pci_x86_write_config,
56 static const struct udevice_id pci_ivybridge_ids[] = {
57 { .compatible = "intel,pci-ivybridge" },
61 U_BOOT_DRIVER(pci_ivybridge_drv) = {
62 .name = "pci_ivybridge",
64 .of_match = pci_ivybridge_ids,
65 .ops = &pci_ivybridge_ops,
66 .probe = pci_ivybridge_probe,