2 * From Coreboot src/northbridge/intel/sandybridge/report_platform.c
4 * Copyright (C) 2012 Google Inc.
6 * SPDX-License-Identifier: GPL-2.0
12 #include <asm/arch/pch.h>
14 static void report_cpu_info(void)
16 char cpu_string[CPU_MAX_NAME_LEN], *cpu_name;
17 const char *mode[] = {"NOT ", ""};
18 struct cpuid_result cpuidr;
23 cpuidr = cpuid(index);
24 if (cpuidr.eax < 0x80000004) {
25 strcpy(cpu_string, "Platform info not available");
26 cpu_name = cpu_string;
28 cpu_name = cpu_get_name(cpu_string);
32 debug("CPU id(%x): %s\n", cpuidr.eax, cpu_name);
33 aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
34 txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
35 vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
36 debug("AES %ssupported, TXT %ssupported, VT %ssupported\n",
37 mode[aes], mode[txt], mode[vt]);
40 /* The PCI id name match comes from Intel document 472178 */
45 {0x1E41, "Desktop Sample"},
46 {0x1E42, "Mobile Sample"},
47 {0x1E43, "SFF Sample"},
66 static void report_pch_info(void)
68 const char *pch_type = "Unknown";
73 dev_id = x86_pci_read_config16(PCH_LPC_DEV, 2);
74 for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
75 if (pch_table[i].dev_id == dev_id) {
76 pch_type = pch_table[i].dev_name;
80 rev_id = x86_pci_read_config8(PCH_LPC_DEV, 8);
81 debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id,
85 void report_platform_info(void)