2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2010,2011
4 * Graeme Russ, <graeme.russ@gmail.com>
6 * Portions from Coreboot mainboard/google/link/romstage.c
7 * Copyright (C) 2007-2010 coresystems GmbH
8 * Copyright (C) 2011 Google Inc.
10 * SPDX-License-Identifier: GPL-2.0
20 #include <spi_flash.h>
21 #include <asm/processor.h>
23 #include <asm/global_data.h>
26 #include <asm/arch/me.h>
27 #include <asm/arch/mrccache.h>
28 #include <asm/arch/pei_data.h>
29 #include <asm/arch/pch.h>
31 #include <asm/arch/sandybridge.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 #define CMOS_OFFSET_MRC_SEED 152
36 #define CMOS_OFFSET_MRC_SEED_S3 156
37 #define CMOS_OFFSET_MRC_SEED_CHK 160
40 * This function looks for the highest region of memory lower than 4GB which
41 * has enough space for U-Boot where U-Boot is aligned on a page boundary.
42 * It overrides the default implementation found elsewhere which simply
43 * picks the end of ram, wherever that may be. The location of the stack,
44 * the relocation address, and how far U-Boot is moved by relocation are
45 * set in the global data structure.
47 ulong board_get_usable_ram_top(ulong total_size)
49 struct memory_info *info = &gd->arch.meminfo;
50 uintptr_t dest_addr = 0;
51 struct memory_area *largest = NULL;
54 /* Find largest area of memory below 4GB */
56 for (i = 0; i < info->num_areas; i++) {
57 struct memory_area *area = &info->area[i];
59 if (area->start >= 1ULL << 32)
61 if (!largest || area->size > largest->size)
65 /* If no suitable area was found, return an error. */
67 if (!largest || largest->size < (2 << 20))
68 panic("No available memory found for relocation");
70 dest_addr = largest->start + largest->size;
72 return (ulong)dest_addr;
75 void dram_init_banksize(void)
77 struct memory_info *info = &gd->arch.meminfo;
81 for (i = 0, num_banks = 0; i < info->num_areas; i++) {
82 struct memory_area *area = &info->area[i];
84 if (area->start >= 1ULL << 32)
86 gd->bd->bi_dram[num_banks].start = area->start;
87 gd->bd->bi_dram[num_banks].size = area->size;
92 static int get_mrc_entry(struct udevice **devp, struct fmap_entry *entry)
94 const void *blob = gd->fdt_blob;
95 int node, spi_node, mrc_node;
99 /* Find the flash chip within the SPI controller node */
101 spi_node = fdtdec_next_alias(blob, "spi", COMPAT_INTEL_ICH_SPI, &upto);
104 node = fdt_first_subnode(blob, spi_node);
108 /* Find the place where we put the MRC cache */
109 mrc_node = fdt_subnode_offset(blob, node, "rw-mrc-cache");
113 if (fdtdec_read_fmap_entry(blob, mrc_node, "rm-mrc-cache", entry))
117 debug("getting sf\n");
118 ret = uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node,
120 debug("ret = %d\n", ret);
128 static int read_seed_from_cmos(struct pei_data *pei_data)
130 u16 c1, c2, checksum, seed_checksum;
134 rcode = uclass_get_device(UCLASS_RTC, 0, &dev);
136 debug("Cannot find RTC: err=%d\n", rcode);
141 * Read scrambler seeds from CMOS RAM. We don't want to store them in
142 * SPI flash since they change on every boot and that would wear down
143 * the flash too much. So we store these in CMOS and the large MRC
146 rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed);
147 debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n",
148 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
150 rtc_read32(dev, CMOS_OFFSET_MRC_SEED_S3, &pei_data->scrambler_seed_s3);
151 debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n",
152 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
154 /* Compute seed checksum and compare */
155 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed,
157 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3,
159 checksum = add_ip_checksums(sizeof(u32), c1, c2);
161 seed_checksum = rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK);
162 seed_checksum |= rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1) << 8;
164 if (checksum != seed_checksum) {
165 debug("%s: invalid seed checksum\n", __func__);
166 pei_data->scrambler_seed = 0;
167 pei_data->scrambler_seed_s3 = 0;
174 static int prepare_mrc_cache(struct pei_data *pei_data)
176 struct mrc_data_container *mrc_cache;
177 struct fmap_entry entry;
180 ret = read_seed_from_cmos(pei_data);
183 ret = get_mrc_entry(NULL, &entry);
186 mrc_cache = mrccache_find_current(&entry);
191 * TODO(sjg@chromium.org): Skip this for now as it causes boot
195 pei_data->mrc_input = mrc_cache->data;
196 pei_data->mrc_input_len = mrc_cache->data_size;
198 debug("%s: at %p, size %x checksum %04x\n", __func__,
199 pei_data->mrc_input, pei_data->mrc_input_len,
200 mrc_cache->checksum);
205 static int build_mrc_data(struct mrc_data_container **datap)
207 struct mrc_data_container *data;
211 orig_len = gd->arch.mrc_output_len;
212 output_len = ALIGN(orig_len, 16);
213 data = malloc(output_len + sizeof(*data));
216 data->signature = MRC_DATA_SIGNATURE;
217 data->data_size = output_len;
219 memcpy(data->data, gd->arch.mrc_output, orig_len);
221 /* Zero the unused space in aligned buffer. */
222 if (output_len > orig_len)
223 memset(data->data + orig_len, 0, output_len - orig_len);
225 data->checksum = compute_ip_checksum(data->data, output_len);
231 static int write_seeds_to_cmos(struct pei_data *pei_data)
233 u16 c1, c2, checksum;
237 rcode = uclass_get_device(UCLASS_RTC, 0, &dev);
239 debug("Cannot find RTC: err=%d\n", rcode);
243 /* Save the MRC seed values to CMOS */
244 rtc_write32(dev, CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
245 debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n",
246 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
248 rtc_write32(dev, CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
249 debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n",
250 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
252 /* Save a simple checksum of the seed values */
253 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed,
255 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3,
257 checksum = add_ip_checksums(sizeof(u32), c1, c2);
259 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff);
260 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff);
265 static int sdram_save_mrc_data(void)
267 struct mrc_data_container *data;
268 struct fmap_entry entry;
272 if (!gd->arch.mrc_output_len)
274 debug("Saving %d bytes of MRC output data to SPI flash\n",
275 gd->arch.mrc_output_len);
277 ret = get_mrc_entry(&sf, &entry);
280 ret = build_mrc_data(&data);
283 ret = mrccache_update(sf, &entry, data);
285 debug("Saved MRC data with checksum %04x\n", data->checksum);
291 debug("%s: Failed: %d\n", __func__, ret);
295 /* Use this hook to save our SDRAM parameters */
296 int misc_init_r(void)
300 ret = sdram_save_mrc_data();
302 printf("Unable to save MRC data: %d\n", ret);
307 static const char *const ecc_decoder[] = {
315 * Dump in the log memory controller configuration as read from the memory
316 * controller registers.
318 static void report_memory_config(void)
320 u32 addr_decoder_common, addr_decode_ch[2];
323 addr_decoder_common = readl(MCHBAR_REG(0x5000));
324 addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
325 addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
327 debug("memcfg DDR3 clock %d MHz\n",
328 (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100);
329 debug("memcfg channel assignment: A: %d, B % d, C % d\n",
330 addr_decoder_common & 3,
331 (addr_decoder_common >> 2) & 3,
332 (addr_decoder_common >> 4) & 3);
334 for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
335 u32 ch_conf = addr_decode_ch[i];
336 debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
337 debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
338 debug(" enhanced interleave mode %s\n",
339 ((ch_conf >> 22) & 1) ? "on" : "off");
340 debug(" rank interleave %s\n",
341 ((ch_conf >> 21) & 1) ? "on" : "off");
342 debug(" DIMMA %d MB width x%d %s rank%s\n",
343 ((ch_conf >> 0) & 0xff) * 256,
344 ((ch_conf >> 19) & 1) ? 16 : 8,
345 ((ch_conf >> 17) & 1) ? "dual" : "single",
346 ((ch_conf >> 16) & 1) ? "" : ", selected");
347 debug(" DIMMB %d MB width x%d %s rank%s\n",
348 ((ch_conf >> 8) & 0xff) * 256,
349 ((ch_conf >> 20) & 1) ? 16 : 8,
350 ((ch_conf >> 18) & 1) ? "dual" : "single",
351 ((ch_conf >> 16) & 1) ? ", selected" : "");
355 static void post_system_agent_init(struct pei_data *pei_data)
357 /* If PCIe init is skipped, set the PEG clock gating */
358 if (!pei_data->pcie_init)
359 setbits_le32(MCHBAR_REG(0x7010), 1);
362 static asmlinkage void console_tx_byte(unsigned char byte)
369 static int recovery_mode_enabled(void)
375 * Find the PEI executable in the ROM and execute it.
377 * @param pei_data: configuration data for UEFI PEI reference code
379 int sdram_initialise(struct pei_data *pei_data)
386 report_platform_info();
388 /* Wait for ME to be ready */
389 ret = intel_early_me_init();
392 ret = intel_early_me_uma_size();
396 debug("Starting UEFI PEI System Agent\n");
399 * Do not pass MRC data in for recovery mode boot,
400 * Always pass it in for S3 resume.
402 if (!recovery_mode_enabled() ||
403 pei_data->boot_mode == PEI_BOOT_RESUME) {
404 ret = prepare_mrc_cache(pei_data);
406 debug("prepare_mrc_cache failed: %d\n", ret);
409 /* If MRC data is not found we cannot continue S3 resume. */
410 if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
411 debug("Giving up in sdram_initialize: No MRC data\n");
415 /* Pass console handler in pei_data */
416 pei_data->tx_byte = console_tx_byte;
418 debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));
420 data = (char *)CONFIG_X86_MRC_ADDR;
423 int (*func)(struct pei_data *);
425 debug("Calling MRC at %p\n", data);
426 post_code(POST_PRE_MRC);
427 func = (int (*)(struct pei_data *))data;
433 printf("PEI version mismatch.\n");
436 printf("Invalid memory frequency.\n");
439 printf("MRC returned %x.\n", rv);
441 printf("Nonzero MRC return value.\n");
445 printf("UEFI PEI System Agent not found.\n");
450 /* mrc.bin reconfigures USB, so reinit it to have debug */
451 early_usbdebug_init();
454 version = readl(MCHBAR_REG(0x5034));
455 debug("System Agent Version %d.%d.%d Build %d\n",
456 version >> 24 , (version >> 16) & 0xff,
457 (version >> 8) & 0xff, version & 0xff);
458 debug("MCR output data length %#x at %p\n", pei_data->mrc_output_len,
459 pei_data->mrc_output);
462 * Send ME init done for SandyBridge here. This is done inside the
463 * SystemAgent binary on IvyBridge
465 done = x86_pci_read_config32(PCH_DEV, PCI_DEVICE_ID);
466 done &= BASE_REV_MASK;
467 if (BASE_REV_SNB == done)
468 intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
470 intel_early_me_status();
472 post_system_agent_init(pei_data);
473 report_memory_config();
475 /* S3 resume: don't save scrambler seed or MRC data */
476 if (pei_data->boot_mode != PEI_BOOT_RESUME) {
478 * This will be copied to SDRAM in reserve_arch(), then written
479 * to SPI flash in sdram_save_mrc_data()
481 gd->arch.mrc_output = (char *)pei_data->mrc_output;
482 gd->arch.mrc_output_len = pei_data->mrc_output_len;
483 ret = write_seeds_to_cmos(pei_data);
485 debug("Failed to write seeds to CMOS: %d\n", ret);
491 int reserve_arch(void)
495 checksum = compute_ip_checksum(gd->arch.mrc_output,
496 gd->arch.mrc_output_len);
497 debug("Saving %d bytes for MRC output data, checksum %04x\n",
498 gd->arch.mrc_output_len, checksum);
499 gd->start_addr_sp -= gd->arch.mrc_output_len;
500 memcpy((void *)gd->start_addr_sp, gd->arch.mrc_output,
501 gd->arch.mrc_output_len);
502 gd->arch.mrc_output = (char *)gd->start_addr_sp;
503 gd->start_addr_sp &= ~0xf;
508 static int copy_spd(struct pei_data *peid)
510 const int gpio_vector[] = {41, 42, 43, 10, -1};
512 const void *blob = gd->fdt_blob;
517 if (gpio_vector[i] == -1)
519 ret = gpio_requestf(gpio_vector[i], "spd_id%d", i);
521 debug("%s: Could not request gpio %d\n", __func__,
526 spd_index = gpio_get_values_as_int(gpio_vector);
527 debug("spd index %d\n", spd_index);
528 node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD);
530 printf("SPD data not found.\n");
534 for (spd_node = fdt_first_subnode(blob, node);
536 spd_node = fdt_next_subnode(blob, spd_node)) {
540 if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index)
542 data = fdt_getprop(blob, spd_node, "data", &len);
543 if (len < sizeof(peid->spd_data[0])) {
544 printf("Missing SPD data\n");
548 debug("Using SDRAM SPD data for '%s'\n",
549 fdt_get_name(blob, spd_node, NULL));
550 memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
555 printf("No SPD data found for index %d\n", spd_index);
563 * add_memory_area() - Add a new usable memory area to our list
565 * Note: @start and @end must not span the first 4GB boundary
567 * @info: Place to store memory info
568 * @start: Start of this memory area
569 * @end: End of this memory area + 1
571 static int add_memory_area(struct memory_info *info,
572 uint64_t start, uint64_t end)
574 struct memory_area *ptr;
576 if (info->num_areas == CONFIG_NR_DRAM_BANKS)
579 ptr = &info->area[info->num_areas];
581 ptr->size = end - start;
582 info->total_memory += ptr->size;
583 if (ptr->start < (1ULL << 32))
584 info->total_32bit_memory += ptr->size;
585 debug("%d: memory %llx size %llx, total now %llx / %llx\n",
586 info->num_areas, ptr->start, ptr->size,
587 info->total_32bit_memory, info->total_memory);
594 * sdram_find() - Find available memory
596 * This is a bit complicated since on x86 there are system memory holes all
597 * over the place. We create a list of available memory blocks
599 static int sdram_find(pci_dev_t dev)
601 struct memory_info *info = &gd->arch.meminfo;
602 uint32_t tseg_base, uma_size, tolud;
603 uint64_t tom, me_base, touud;
604 uint64_t uma_memory_base = 0;
605 uint64_t uma_memory_size;
606 unsigned long long tomk;
609 /* Total Memory 2GB example:
611 * 00000000 0000MB-1992MB 1992MB RAM (writeback)
612 * 7c800000 1992MB-2000MB 8MB TSEG (SMRR)
613 * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached)
614 * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached)
615 * 7f200000 2034MB TOLUD
616 * 7f800000 2040MB MEBASE
617 * 7f800000 2040MB-2048MB 8MB ME UMA (uncached)
618 * 80000000 2048MB TOM
619 * 100000000 4096MB-4102MB 6MB RAM (writeback)
621 * Total Memory 4GB example:
623 * 00000000 0000MB-2768MB 2768MB RAM (writeback)
624 * ad000000 2768MB-2776MB 8MB TSEG (SMRR)
625 * ad800000 2776MB-2778MB 2MB GFX GTT (uncached)
626 * ada00000 2778MB-2810MB 32MB GFX UMA (uncached)
627 * afa00000 2810MB TOLUD
628 * ff800000 4088MB MEBASE
629 * ff800000 4088MB-4096MB 8MB ME UMA (uncached)
630 * 100000000 4096MB TOM
631 * 100000000 4096MB-5374MB 1278MB RAM (writeback)
632 * 14fe00000 5368MB TOUUD
635 /* Top of Upper Usable DRAM, including remap */
636 touud = x86_pci_read_config32(dev, TOUUD+4);
638 touud |= x86_pci_read_config32(dev, TOUUD);
640 /* Top of Lower Usable DRAM */
641 tolud = x86_pci_read_config32(dev, TOLUD);
643 /* Top of Memory - does not account for any UMA */
644 tom = x86_pci_read_config32(dev, 0xa4);
646 tom |= x86_pci_read_config32(dev, 0xa0);
648 debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom);
650 /* ME UMA needs excluding if total memory <4GB */
651 me_base = x86_pci_read_config32(dev, 0x74);
653 me_base |= x86_pci_read_config32(dev, 0x70);
655 debug("MEBASE %llx\n", me_base);
657 /* TODO: Get rid of all this shifting by 10 bits */
659 if (me_base == tolud) {
660 /* ME is from MEBASE-TOM */
661 uma_size = (tom - me_base) >> 10;
662 /* Increment TOLUD to account for ME as RAM */
663 tolud += uma_size << 10;
664 /* UMA starts at old TOLUD */
665 uma_memory_base = tomk * 1024ULL;
666 uma_memory_size = uma_size * 1024ULL;
667 debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10);
670 /* Graphics memory comes next */
671 ggc = x86_pci_read_config16(dev, GGC);
673 debug("IGD decoded, subtracting ");
675 /* Graphics memory */
676 uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL;
677 debug("%uM UMA", uma_size >> 10);
679 uma_memory_base = tomk * 1024ULL;
680 uma_memory_size += uma_size * 1024ULL;
682 /* GTT Graphics Stolen Memory Size (GGMS) */
683 uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
685 uma_memory_base = tomk * 1024ULL;
686 uma_memory_size += uma_size * 1024ULL;
687 debug(" and %uM GTT\n", uma_size >> 10);
690 /* Calculate TSEG size from its base which must be below GTT */
691 tseg_base = x86_pci_read_config32(dev, 0xb8);
692 uma_size = (uma_memory_base - tseg_base) >> 10;
694 uma_memory_base = tomk * 1024ULL;
695 uma_memory_size += uma_size * 1024ULL;
696 debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10);
698 debug("Available memory below 4GB: %lluM\n", tomk >> 10);
700 /* Report the memory regions */
701 add_memory_area(info, 1 << 20, 2 << 28);
702 add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
703 add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
704 add_memory_area(info, 1ULL << 32, touud);
706 /* Add MTRRs for memory */
707 mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
708 mtrr_add_request(MTRR_TYPE_WRBACK, 2ULL << 30, 512 << 20);
709 mtrr_add_request(MTRR_TYPE_WRBACK, 0xaULL << 28, 256 << 20);
710 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base, 16 << 20);
711 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base + (16 << 20),
715 * If >= 4GB installed then memory from TOLUD to 4GB
716 * is remapped above TOM, TOUUD will account for both
718 if (touud > (1ULL << 32ULL)) {
719 debug("Available memory above 4GB: %lluM\n",
720 (touud >> 20) - 4096);
726 static void rcba_config(void)
729 * GFX INTA -> PIRQA (MSI)
730 * D28IP_P3IP WLAN INTA -> PIRQB
731 * D29IP_E1P EHCI1 INTA -> PIRQD
732 * D26IP_E2P EHCI2 INTA -> PIRQF
733 * D31IP_SIP SATA INTA -> PIRQF (MSI)
734 * D31IP_SMIP SMBUS INTB -> PIRQH
735 * D31IP_TTIP THRT INTC -> PIRQA
736 * D27IP_ZIP HDA INTA -> PIRQA (MSI)
738 * TRACKPAD -> PIRQE (Edge Triggered)
739 * TOUCHSCREEN -> PIRQG (Edge Triggered)
742 /* Device interrupt pin register (board specific) */
743 writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
744 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP));
745 writel(NOINT << D30IP_PIP, RCB_REG(D30IP));
746 writel(INTA << D29IP_E1P, RCB_REG(D29IP));
747 writel(INTA << D28IP_P3IP, RCB_REG(D28IP));
748 writel(INTA << D27IP_ZIP, RCB_REG(D27IP));
749 writel(INTA << D26IP_E2P, RCB_REG(D26IP));
750 writel(NOINT << D25IP_LIP, RCB_REG(D25IP));
751 writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP));
753 /* Device interrupt route registers */
754 writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR));
755 writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR));
756 writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR));
757 writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR));
758 writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR));
759 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR));
760 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR));
762 /* Enable IOAPIC (generic) */
763 writew(0x0100, RCB_REG(OIC));
764 /* PCH BWG says to read back the IOAPIC enable register */
765 (void)readw(RCB_REG(OIC));
767 /* Disable unused devices (board specific) */
768 setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS);
773 struct pei_data pei_data __aligned(8) = {
774 .pei_version = PEI_VERSION,
775 .mchbar = DEFAULT_MCHBAR,
776 .dmibar = DEFAULT_DMIBAR,
777 .epbar = DEFAULT_EPBAR,
778 .pciexbar = CONFIG_PCIE_ECAM_BASE,
779 .smbusbar = SMBUS_IO_BASE,
782 .hpet_address = CONFIG_HPET_ADDRESS,
783 .rcba = DEFAULT_RCBABASE,
784 .pmbase = DEFAULT_PMBASE,
785 .gpiobase = DEFAULT_GPIOBASE,
786 .thermalbase = 0xfed08000,
787 .system_type = 0, /* 0 Mobile, 1 Desktop/Server */
788 .tseg_size = CONFIG_SMM_TSEG_SIZE,
789 .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
793 * 0 = leave channel enabled
794 * 1 = disable dimm 0 on channel
795 * 2 = disable dimm 1 on channel
796 * 3 = disable dimm 0+1 on channel
798 .dimm_channel0_disabled = 2,
799 .dimm_channel1_disabled = 2,
800 .max_ddr3_freq = 1600,
803 * Empty and onboard Ports 0-7, set to un-used pin
806 { 0, 3, 0x0000 }, /* P0= Empty */
807 { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */
808 { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */
809 { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */
810 { 0, 3, 0x0000 }, /* P4= Empty */
811 { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */
812 { 0, 3, 0x0000 }, /* P6= Empty */
813 { 0, 3, 0x0000 }, /* P7= Empty */
815 * Empty and onboard Ports 8-13, set to un-used pin
818 { 1, 4, 0x0040 }, /* P8= Camera (no OC) */
819 { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */
820 { 0, 4, 0x0000 }, /* P10= Empty */
821 { 0, 4, 0x0000 }, /* P11= Empty */
822 { 0, 4, 0x0000 }, /* P12= Empty */
823 { 0, 4, 0x0000 }, /* P13= Empty */
826 pci_dev_t dev = PCI_BDF(0, 0, 0);
829 debug("Boot mode %d\n", gd->arch.pei_boot_mode);
830 debug("mcr_input %p\n", pei_data.mrc_input);
831 pei_data.boot_mode = gd->arch.pei_boot_mode;
832 ret = copy_spd(&pei_data);
834 ret = sdram_initialise(&pei_data);
841 writew(0xCAFE, MCHBAR_REG(SSKPD));
843 post_code(POST_DRAM);
845 ret = sdram_find(dev);
849 gd->ram_size = gd->arch.meminfo.total_32bit_memory;