2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2010,2011
4 * Graeme Russ, <graeme.russ@gmail.com>
6 * Portions from Coreboot mainboard/google/link/romstage.c
7 * Copyright (C) 2007-2010 coresystems GmbH
8 * Copyright (C) 2011 Google Inc.
10 * SPDX-License-Identifier: GPL-2.0
20 #include <spi_flash.h>
21 #include <asm/processor.h>
23 #include <asm/global_data.h>
26 #include <asm/arch/me.h>
27 #include <asm/arch/mrccache.h>
28 #include <asm/arch/pei_data.h>
29 #include <asm/arch/pch.h>
31 #include <asm/arch/sandybridge.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 #define CMOS_OFFSET_MRC_SEED 152
36 #define CMOS_OFFSET_MRC_SEED_S3 156
37 #define CMOS_OFFSET_MRC_SEED_CHK 160
40 * This function looks for the highest region of memory lower than 4GB which
41 * has enough space for U-Boot where U-Boot is aligned on a page boundary.
42 * It overrides the default implementation found elsewhere which simply
43 * picks the end of ram, wherever that may be. The location of the stack,
44 * the relocation address, and how far U-Boot is moved by relocation are
45 * set in the global data structure.
47 ulong board_get_usable_ram_top(ulong total_size)
49 struct memory_info *info = &gd->arch.meminfo;
50 uintptr_t dest_addr = 0;
51 struct memory_area *largest = NULL;
54 /* Find largest area of memory below 4GB */
56 for (i = 0; i < info->num_areas; i++) {
57 struct memory_area *area = &info->area[i];
59 if (area->start >= 1ULL << 32)
61 if (!largest || area->size > largest->size)
65 /* If no suitable area was found, return an error. */
67 if (!largest || largest->size < (2 << 20))
68 panic("No available memory found for relocation");
70 dest_addr = largest->start + largest->size;
72 return (ulong)dest_addr;
75 void dram_init_banksize(void)
77 struct memory_info *info = &gd->arch.meminfo;
81 for (i = 0, num_banks = 0; i < info->num_areas; i++) {
82 struct memory_area *area = &info->area[i];
84 if (area->start >= 1ULL << 32)
86 gd->bd->bi_dram[num_banks].start = area->start;
87 gd->bd->bi_dram[num_banks].size = area->size;
92 static int get_mrc_entry(struct udevice **devp, struct fmap_entry *entry)
94 const void *blob = gd->fdt_blob;
95 int node, spi_node, mrc_node;
99 /* Find the flash chip within the SPI controller node */
101 spi_node = fdtdec_next_alias(blob, "spi", COMPAT_INTEL_ICH_SPI, &upto);
104 node = fdt_first_subnode(blob, spi_node);
108 /* Find the place where we put the MRC cache */
109 mrc_node = fdt_subnode_offset(blob, node, "rw-mrc-cache");
113 if (fdtdec_read_fmap_entry(blob, mrc_node, "rm-mrc-cache", entry))
117 debug("getting sf\n");
118 ret = uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node,
120 debug("ret = %d\n", ret);
128 static int read_seed_from_cmos(struct pei_data *pei_data)
130 u16 c1, c2, checksum, seed_checksum;
133 * Read scrambler seeds from CMOS RAM. We don't want to store them in
134 * SPI flash since they change on every boot and that would wear down
135 * the flash too much. So we store these in CMOS and the large MRC
138 pei_data->scrambler_seed = rtc_read32(CMOS_OFFSET_MRC_SEED);
139 debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n",
140 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
142 pei_data->scrambler_seed_s3 = rtc_read32(CMOS_OFFSET_MRC_SEED_S3);
143 debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n",
144 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
146 /* Compute seed checksum and compare */
147 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed,
149 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3,
151 checksum = add_ip_checksums(sizeof(u32), c1, c2);
153 seed_checksum = rtc_read8(CMOS_OFFSET_MRC_SEED_CHK);
154 seed_checksum |= rtc_read8(CMOS_OFFSET_MRC_SEED_CHK + 1) << 8;
156 if (checksum != seed_checksum) {
157 debug("%s: invalid seed checksum\n", __func__);
158 pei_data->scrambler_seed = 0;
159 pei_data->scrambler_seed_s3 = 0;
166 static int prepare_mrc_cache(struct pei_data *pei_data)
168 struct mrc_data_container *mrc_cache;
169 struct fmap_entry entry;
172 ret = read_seed_from_cmos(pei_data);
175 ret = get_mrc_entry(NULL, &entry);
178 mrc_cache = mrccache_find_current(&entry);
183 * TODO(sjg@chromium.org): Skip this for now as it causes boot
187 pei_data->mrc_input = mrc_cache->data;
188 pei_data->mrc_input_len = mrc_cache->data_size;
190 debug("%s: at %p, size %x checksum %04x\n", __func__,
191 pei_data->mrc_input, pei_data->mrc_input_len,
192 mrc_cache->checksum);
197 static int build_mrc_data(struct mrc_data_container **datap)
199 struct mrc_data_container *data;
203 orig_len = gd->arch.mrc_output_len;
204 output_len = ALIGN(orig_len, 16);
205 data = malloc(output_len + sizeof(*data));
208 data->signature = MRC_DATA_SIGNATURE;
209 data->data_size = output_len;
211 memcpy(data->data, gd->arch.mrc_output, orig_len);
213 /* Zero the unused space in aligned buffer. */
214 if (output_len > orig_len)
215 memset(data->data + orig_len, 0, output_len - orig_len);
217 data->checksum = compute_ip_checksum(data->data, output_len);
223 static int write_seeds_to_cmos(struct pei_data *pei_data)
225 u16 c1, c2, checksum;
227 /* Save the MRC seed values to CMOS */
228 rtc_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
229 debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n",
230 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
232 rtc_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
233 debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n",
234 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
236 /* Save a simple checksum of the seed values */
237 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed,
239 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3,
241 checksum = add_ip_checksums(sizeof(u32), c1, c2);
243 rtc_write8(CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff);
244 rtc_write8(CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff);
249 static int sdram_save_mrc_data(void)
251 struct mrc_data_container *data;
252 struct fmap_entry entry;
256 if (!gd->arch.mrc_output_len)
258 debug("Saving %d bytes of MRC output data to SPI flash\n",
259 gd->arch.mrc_output_len);
261 ret = get_mrc_entry(&sf, &entry);
264 ret = build_mrc_data(&data);
267 ret = mrccache_update(sf, &entry, data);
269 debug("Saved MRC data with checksum %04x\n", data->checksum);
275 debug("%s: Failed: %d\n", __func__, ret);
279 /* Use this hook to save our SDRAM parameters */
280 int misc_init_r(void)
284 ret = sdram_save_mrc_data();
286 printf("Unable to save MRC data: %d\n", ret);
291 static const char *const ecc_decoder[] = {
299 * Dump in the log memory controller configuration as read from the memory
300 * controller registers.
302 static void report_memory_config(void)
304 u32 addr_decoder_common, addr_decode_ch[2];
307 addr_decoder_common = readl(MCHBAR_REG(0x5000));
308 addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
309 addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
311 debug("memcfg DDR3 clock %d MHz\n",
312 (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100);
313 debug("memcfg channel assignment: A: %d, B % d, C % d\n",
314 addr_decoder_common & 3,
315 (addr_decoder_common >> 2) & 3,
316 (addr_decoder_common >> 4) & 3);
318 for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
319 u32 ch_conf = addr_decode_ch[i];
320 debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
321 debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
322 debug(" enhanced interleave mode %s\n",
323 ((ch_conf >> 22) & 1) ? "on" : "off");
324 debug(" rank interleave %s\n",
325 ((ch_conf >> 21) & 1) ? "on" : "off");
326 debug(" DIMMA %d MB width x%d %s rank%s\n",
327 ((ch_conf >> 0) & 0xff) * 256,
328 ((ch_conf >> 19) & 1) ? 16 : 8,
329 ((ch_conf >> 17) & 1) ? "dual" : "single",
330 ((ch_conf >> 16) & 1) ? "" : ", selected");
331 debug(" DIMMB %d MB width x%d %s rank%s\n",
332 ((ch_conf >> 8) & 0xff) * 256,
333 ((ch_conf >> 20) & 1) ? 16 : 8,
334 ((ch_conf >> 18) & 1) ? "dual" : "single",
335 ((ch_conf >> 16) & 1) ? ", selected" : "");
339 static void post_system_agent_init(struct pei_data *pei_data)
341 /* If PCIe init is skipped, set the PEG clock gating */
342 if (!pei_data->pcie_init)
343 setbits_le32(MCHBAR_REG(0x7010), 1);
346 static asmlinkage void console_tx_byte(unsigned char byte)
353 static int recovery_mode_enabled(void)
359 * Find the PEI executable in the ROM and execute it.
361 * @param pei_data: configuration data for UEFI PEI reference code
363 int sdram_initialise(struct pei_data *pei_data)
370 report_platform_info();
372 /* Wait for ME to be ready */
373 ret = intel_early_me_init();
376 ret = intel_early_me_uma_size();
380 debug("Starting UEFI PEI System Agent\n");
383 * Do not pass MRC data in for recovery mode boot,
384 * Always pass it in for S3 resume.
386 if (!recovery_mode_enabled() ||
387 pei_data->boot_mode == PEI_BOOT_RESUME) {
388 ret = prepare_mrc_cache(pei_data);
390 debug("prepare_mrc_cache failed: %d\n", ret);
393 /* If MRC data is not found we cannot continue S3 resume. */
394 if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
395 debug("Giving up in sdram_initialize: No MRC data\n");
399 /* Pass console handler in pei_data */
400 pei_data->tx_byte = console_tx_byte;
402 debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));
404 data = (char *)CONFIG_X86_MRC_ADDR;
407 int (*func)(struct pei_data *);
409 debug("Calling MRC at %p\n", data);
410 post_code(POST_PRE_MRC);
411 func = (int (*)(struct pei_data *))data;
417 printf("PEI version mismatch.\n");
420 printf("Invalid memory frequency.\n");
423 printf("MRC returned %x.\n", rv);
425 printf("Nonzero MRC return value.\n");
429 printf("UEFI PEI System Agent not found.\n");
434 /* mrc.bin reconfigures USB, so reinit it to have debug */
435 early_usbdebug_init();
438 version = readl(MCHBAR_REG(0x5034));
439 debug("System Agent Version %d.%d.%d Build %d\n",
440 version >> 24 , (version >> 16) & 0xff,
441 (version >> 8) & 0xff, version & 0xff);
442 debug("MCR output data length %#x at %p\n", pei_data->mrc_output_len,
443 pei_data->mrc_output);
446 * Send ME init done for SandyBridge here. This is done inside the
447 * SystemAgent binary on IvyBridge
449 done = x86_pci_read_config32(PCH_DEV, PCI_DEVICE_ID);
450 done &= BASE_REV_MASK;
451 if (BASE_REV_SNB == done)
452 intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
454 intel_early_me_status();
456 post_system_agent_init(pei_data);
457 report_memory_config();
459 /* S3 resume: don't save scrambler seed or MRC data */
460 if (pei_data->boot_mode != PEI_BOOT_RESUME) {
462 * This will be copied to SDRAM in reserve_arch(), then written
463 * to SPI flash in sdram_save_mrc_data()
465 gd->arch.mrc_output = (char *)pei_data->mrc_output;
466 gd->arch.mrc_output_len = pei_data->mrc_output_len;
467 ret = write_seeds_to_cmos(pei_data);
469 debug("Failed to write seeds to CMOS: %d\n", ret);
475 int reserve_arch(void)
479 checksum = compute_ip_checksum(gd->arch.mrc_output,
480 gd->arch.mrc_output_len);
481 debug("Saving %d bytes for MRC output data, checksum %04x\n",
482 gd->arch.mrc_output_len, checksum);
483 gd->start_addr_sp -= gd->arch.mrc_output_len;
484 memcpy((void *)gd->start_addr_sp, gd->arch.mrc_output,
485 gd->arch.mrc_output_len);
486 gd->arch.mrc_output = (char *)gd->start_addr_sp;
487 gd->start_addr_sp &= ~0xf;
492 static int copy_spd(struct pei_data *peid)
494 const int gpio_vector[] = {41, 42, 43, 10, -1};
496 const void *blob = gd->fdt_blob;
501 if (gpio_vector[i] == -1)
503 ret = gpio_requestf(gpio_vector[i], "spd_id%d", i);
505 debug("%s: Could not request gpio %d\n", __func__,
510 spd_index = gpio_get_values_as_int(gpio_vector);
511 debug("spd index %d\n", spd_index);
512 node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD);
514 printf("SPD data not found.\n");
518 for (spd_node = fdt_first_subnode(blob, node);
520 spd_node = fdt_next_subnode(blob, spd_node)) {
524 if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index)
526 data = fdt_getprop(blob, spd_node, "data", &len);
527 if (len < sizeof(peid->spd_data[0])) {
528 printf("Missing SPD data\n");
532 debug("Using SDRAM SPD data for '%s'\n",
533 fdt_get_name(blob, spd_node, NULL));
534 memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
539 printf("No SPD data found for index %d\n", spd_index);
547 * add_memory_area() - Add a new usable memory area to our list
549 * Note: @start and @end must not span the first 4GB boundary
551 * @info: Place to store memory info
552 * @start: Start of this memory area
553 * @end: End of this memory area + 1
555 static int add_memory_area(struct memory_info *info,
556 uint64_t start, uint64_t end)
558 struct memory_area *ptr;
560 if (info->num_areas == CONFIG_NR_DRAM_BANKS)
563 ptr = &info->area[info->num_areas];
565 ptr->size = end - start;
566 info->total_memory += ptr->size;
567 if (ptr->start < (1ULL << 32))
568 info->total_32bit_memory += ptr->size;
569 debug("%d: memory %llx size %llx, total now %llx / %llx\n",
570 info->num_areas, ptr->start, ptr->size,
571 info->total_32bit_memory, info->total_memory);
578 * sdram_find() - Find available memory
580 * This is a bit complicated since on x86 there are system memory holes all
581 * over the place. We create a list of available memory blocks
583 static int sdram_find(pci_dev_t dev)
585 struct memory_info *info = &gd->arch.meminfo;
586 uint32_t tseg_base, uma_size, tolud;
587 uint64_t tom, me_base, touud;
588 uint64_t uma_memory_base = 0;
589 uint64_t uma_memory_size;
590 unsigned long long tomk;
593 /* Total Memory 2GB example:
595 * 00000000 0000MB-1992MB 1992MB RAM (writeback)
596 * 7c800000 1992MB-2000MB 8MB TSEG (SMRR)
597 * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached)
598 * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached)
599 * 7f200000 2034MB TOLUD
600 * 7f800000 2040MB MEBASE
601 * 7f800000 2040MB-2048MB 8MB ME UMA (uncached)
602 * 80000000 2048MB TOM
603 * 100000000 4096MB-4102MB 6MB RAM (writeback)
605 * Total Memory 4GB example:
607 * 00000000 0000MB-2768MB 2768MB RAM (writeback)
608 * ad000000 2768MB-2776MB 8MB TSEG (SMRR)
609 * ad800000 2776MB-2778MB 2MB GFX GTT (uncached)
610 * ada00000 2778MB-2810MB 32MB GFX UMA (uncached)
611 * afa00000 2810MB TOLUD
612 * ff800000 4088MB MEBASE
613 * ff800000 4088MB-4096MB 8MB ME UMA (uncached)
614 * 100000000 4096MB TOM
615 * 100000000 4096MB-5374MB 1278MB RAM (writeback)
616 * 14fe00000 5368MB TOUUD
619 /* Top of Upper Usable DRAM, including remap */
620 touud = x86_pci_read_config32(dev, TOUUD+4);
622 touud |= x86_pci_read_config32(dev, TOUUD);
624 /* Top of Lower Usable DRAM */
625 tolud = x86_pci_read_config32(dev, TOLUD);
627 /* Top of Memory - does not account for any UMA */
628 tom = x86_pci_read_config32(dev, 0xa4);
630 tom |= x86_pci_read_config32(dev, 0xa0);
632 debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom);
634 /* ME UMA needs excluding if total memory <4GB */
635 me_base = x86_pci_read_config32(dev, 0x74);
637 me_base |= x86_pci_read_config32(dev, 0x70);
639 debug("MEBASE %llx\n", me_base);
641 /* TODO: Get rid of all this shifting by 10 bits */
643 if (me_base == tolud) {
644 /* ME is from MEBASE-TOM */
645 uma_size = (tom - me_base) >> 10;
646 /* Increment TOLUD to account for ME as RAM */
647 tolud += uma_size << 10;
648 /* UMA starts at old TOLUD */
649 uma_memory_base = tomk * 1024ULL;
650 uma_memory_size = uma_size * 1024ULL;
651 debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10);
654 /* Graphics memory comes next */
655 ggc = x86_pci_read_config16(dev, GGC);
657 debug("IGD decoded, subtracting ");
659 /* Graphics memory */
660 uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL;
661 debug("%uM UMA", uma_size >> 10);
663 uma_memory_base = tomk * 1024ULL;
664 uma_memory_size += uma_size * 1024ULL;
666 /* GTT Graphics Stolen Memory Size (GGMS) */
667 uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
669 uma_memory_base = tomk * 1024ULL;
670 uma_memory_size += uma_size * 1024ULL;
671 debug(" and %uM GTT\n", uma_size >> 10);
674 /* Calculate TSEG size from its base which must be below GTT */
675 tseg_base = x86_pci_read_config32(dev, 0xb8);
676 uma_size = (uma_memory_base - tseg_base) >> 10;
678 uma_memory_base = tomk * 1024ULL;
679 uma_memory_size += uma_size * 1024ULL;
680 debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10);
682 debug("Available memory below 4GB: %lluM\n", tomk >> 10);
684 /* Report the memory regions */
685 add_memory_area(info, 1 << 20, 2 << 28);
686 add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
687 add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
688 add_memory_area(info, 1ULL << 32, touud);
690 /* Add MTRRs for memory */
691 mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
692 mtrr_add_request(MTRR_TYPE_WRBACK, 2ULL << 30, 512 << 20);
693 mtrr_add_request(MTRR_TYPE_WRBACK, 0xaULL << 28, 256 << 20);
694 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base, 16 << 20);
695 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base + (16 << 20),
699 * If >= 4GB installed then memory from TOLUD to 4GB
700 * is remapped above TOM, TOUUD will account for both
702 if (touud > (1ULL << 32ULL)) {
703 debug("Available memory above 4GB: %lluM\n",
704 (touud >> 20) - 4096);
710 static void rcba_config(void)
713 * GFX INTA -> PIRQA (MSI)
714 * D28IP_P3IP WLAN INTA -> PIRQB
715 * D29IP_E1P EHCI1 INTA -> PIRQD
716 * D26IP_E2P EHCI2 INTA -> PIRQF
717 * D31IP_SIP SATA INTA -> PIRQF (MSI)
718 * D31IP_SMIP SMBUS INTB -> PIRQH
719 * D31IP_TTIP THRT INTC -> PIRQA
720 * D27IP_ZIP HDA INTA -> PIRQA (MSI)
722 * TRACKPAD -> PIRQE (Edge Triggered)
723 * TOUCHSCREEN -> PIRQG (Edge Triggered)
726 /* Device interrupt pin register (board specific) */
727 writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
728 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP));
729 writel(NOINT << D30IP_PIP, RCB_REG(D30IP));
730 writel(INTA << D29IP_E1P, RCB_REG(D29IP));
731 writel(INTA << D28IP_P3IP, RCB_REG(D28IP));
732 writel(INTA << D27IP_ZIP, RCB_REG(D27IP));
733 writel(INTA << D26IP_E2P, RCB_REG(D26IP));
734 writel(NOINT << D25IP_LIP, RCB_REG(D25IP));
735 writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP));
737 /* Device interrupt route registers */
738 writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR));
739 writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR));
740 writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR));
741 writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR));
742 writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR));
743 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR));
744 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR));
746 /* Enable IOAPIC (generic) */
747 writew(0x0100, RCB_REG(OIC));
748 /* PCH BWG says to read back the IOAPIC enable register */
749 (void)readw(RCB_REG(OIC));
751 /* Disable unused devices (board specific) */
752 setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS);
757 struct pei_data pei_data __aligned(8) = {
758 .pei_version = PEI_VERSION,
759 .mchbar = DEFAULT_MCHBAR,
760 .dmibar = DEFAULT_DMIBAR,
761 .epbar = DEFAULT_EPBAR,
762 .pciexbar = CONFIG_PCIE_ECAM_BASE,
763 .smbusbar = SMBUS_IO_BASE,
766 .hpet_address = CONFIG_HPET_ADDRESS,
767 .rcba = DEFAULT_RCBABASE,
768 .pmbase = DEFAULT_PMBASE,
769 .gpiobase = DEFAULT_GPIOBASE,
770 .thermalbase = 0xfed08000,
771 .system_type = 0, /* 0 Mobile, 1 Desktop/Server */
772 .tseg_size = CONFIG_SMM_TSEG_SIZE,
773 .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
777 * 0 = leave channel enabled
778 * 1 = disable dimm 0 on channel
779 * 2 = disable dimm 1 on channel
780 * 3 = disable dimm 0+1 on channel
782 .dimm_channel0_disabled = 2,
783 .dimm_channel1_disabled = 2,
784 .max_ddr3_freq = 1600,
787 * Empty and onboard Ports 0-7, set to un-used pin
790 { 0, 3, 0x0000 }, /* P0= Empty */
791 { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */
792 { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */
793 { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */
794 { 0, 3, 0x0000 }, /* P4= Empty */
795 { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */
796 { 0, 3, 0x0000 }, /* P6= Empty */
797 { 0, 3, 0x0000 }, /* P7= Empty */
799 * Empty and onboard Ports 8-13, set to un-used pin
802 { 1, 4, 0x0040 }, /* P8= Camera (no OC) */
803 { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */
804 { 0, 4, 0x0000 }, /* P10= Empty */
805 { 0, 4, 0x0000 }, /* P11= Empty */
806 { 0, 4, 0x0000 }, /* P12= Empty */
807 { 0, 4, 0x0000 }, /* P13= Empty */
810 pci_dev_t dev = PCI_BDF(0, 0, 0);
813 debug("Boot mode %d\n", gd->arch.pei_boot_mode);
814 debug("mcr_input %p\n", pei_data.mrc_input);
815 pei_data.boot_mode = gd->arch.pei_boot_mode;
816 ret = copy_spd(&pei_data);
818 ret = sdram_initialise(&pei_data);
825 writew(0xCAFE, MCHBAR_REG(SSKPD));
827 post_code(POST_DRAM);
829 ret = sdram_find(dev);
833 gd->ram_size = gd->arch.meminfo.total_32bit_memory;