2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2010,2011
4 * Graeme Russ, <graeme.russ@gmail.com>
6 * Portions from Coreboot mainboard/google/link/romstage.c
7 * Copyright (C) 2007-2010 coresystems GmbH
8 * Copyright (C) 2011 Google Inc.
10 * SPDX-License-Identifier: GPL-2.0
20 #include <spi_flash.h>
21 #include <asm/processor.h>
23 #include <asm/global_data.h>
24 #include <asm/mrccache.h>
27 #include <asm/arch/me.h>
28 #include <asm/arch/pei_data.h>
29 #include <asm/arch/pch.h>
31 #include <asm/arch/sandybridge.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 #define CMOS_OFFSET_MRC_SEED 152
36 #define CMOS_OFFSET_MRC_SEED_S3 156
37 #define CMOS_OFFSET_MRC_SEED_CHK 160
40 * This function looks for the highest region of memory lower than 4GB which
41 * has enough space for U-Boot where U-Boot is aligned on a page boundary.
42 * It overrides the default implementation found elsewhere which simply
43 * picks the end of ram, wherever that may be. The location of the stack,
44 * the relocation address, and how far U-Boot is moved by relocation are
45 * set in the global data structure.
47 ulong board_get_usable_ram_top(ulong total_size)
49 struct memory_info *info = &gd->arch.meminfo;
50 uintptr_t dest_addr = 0;
51 struct memory_area *largest = NULL;
54 /* Find largest area of memory below 4GB */
56 for (i = 0; i < info->num_areas; i++) {
57 struct memory_area *area = &info->area[i];
59 if (area->start >= 1ULL << 32)
61 if (!largest || area->size > largest->size)
65 /* If no suitable area was found, return an error. */
67 if (!largest || largest->size < (2 << 20))
68 panic("No available memory found for relocation");
70 dest_addr = largest->start + largest->size;
72 return (ulong)dest_addr;
75 void dram_init_banksize(void)
77 struct memory_info *info = &gd->arch.meminfo;
81 for (i = 0, num_banks = 0; i < info->num_areas; i++) {
82 struct memory_area *area = &info->area[i];
84 if (area->start >= 1ULL << 32)
86 gd->bd->bi_dram[num_banks].start = area->start;
87 gd->bd->bi_dram[num_banks].size = area->size;
92 static int read_seed_from_cmos(struct pei_data *pei_data)
94 u16 c1, c2, checksum, seed_checksum;
98 rcode = uclass_get_device(UCLASS_RTC, 0, &dev);
100 debug("Cannot find RTC: err=%d\n", rcode);
105 * Read scrambler seeds from CMOS RAM. We don't want to store them in
106 * SPI flash since they change on every boot and that would wear down
107 * the flash too much. So we store these in CMOS and the large MRC
110 rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed);
111 debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n",
112 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
114 rtc_read32(dev, CMOS_OFFSET_MRC_SEED_S3, &pei_data->scrambler_seed_s3);
115 debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n",
116 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
118 /* Compute seed checksum and compare */
119 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed,
121 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3,
123 checksum = add_ip_checksums(sizeof(u32), c1, c2);
125 seed_checksum = rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK);
126 seed_checksum |= rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1) << 8;
128 if (checksum != seed_checksum) {
129 debug("%s: invalid seed checksum\n", __func__);
130 pei_data->scrambler_seed = 0;
131 pei_data->scrambler_seed_s3 = 0;
138 static int prepare_mrc_cache(struct pei_data *pei_data)
140 struct mrc_data_container *mrc_cache;
141 struct mrc_region entry;
144 ret = read_seed_from_cmos(pei_data);
147 ret = mrccache_get_region(NULL, &entry);
150 mrc_cache = mrccache_find_current(&entry);
155 * TODO(sjg@chromium.org): Skip this for now as it causes boot
159 pei_data->mrc_input = mrc_cache->data;
160 pei_data->mrc_input_len = mrc_cache->data_size;
162 debug("%s: at %p, size %x checksum %04x\n", __func__,
163 pei_data->mrc_input, pei_data->mrc_input_len,
164 mrc_cache->checksum);
169 static int write_seeds_to_cmos(struct pei_data *pei_data)
171 u16 c1, c2, checksum;
175 rcode = uclass_get_device(UCLASS_RTC, 0, &dev);
177 debug("Cannot find RTC: err=%d\n", rcode);
181 /* Save the MRC seed values to CMOS */
182 rtc_write32(dev, CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
183 debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n",
184 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
186 rtc_write32(dev, CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
187 debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n",
188 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
190 /* Save a simple checksum of the seed values */
191 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed,
193 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3,
195 checksum = add_ip_checksums(sizeof(u32), c1, c2);
197 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff);
198 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff);
203 /* Use this hook to save our SDRAM parameters */
204 int misc_init_r(void)
208 ret = mrccache_save();
210 printf("Unable to save MRC data: %d\n", ret);
215 static const char *const ecc_decoder[] = {
223 * Dump in the log memory controller configuration as read from the memory
224 * controller registers.
226 static void report_memory_config(void)
228 u32 addr_decoder_common, addr_decode_ch[2];
231 addr_decoder_common = readl(MCHBAR_REG(0x5000));
232 addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
233 addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
235 debug("memcfg DDR3 clock %d MHz\n",
236 (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100);
237 debug("memcfg channel assignment: A: %d, B % d, C % d\n",
238 addr_decoder_common & 3,
239 (addr_decoder_common >> 2) & 3,
240 (addr_decoder_common >> 4) & 3);
242 for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
243 u32 ch_conf = addr_decode_ch[i];
244 debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
245 debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
246 debug(" enhanced interleave mode %s\n",
247 ((ch_conf >> 22) & 1) ? "on" : "off");
248 debug(" rank interleave %s\n",
249 ((ch_conf >> 21) & 1) ? "on" : "off");
250 debug(" DIMMA %d MB width x%d %s rank%s\n",
251 ((ch_conf >> 0) & 0xff) * 256,
252 ((ch_conf >> 19) & 1) ? 16 : 8,
253 ((ch_conf >> 17) & 1) ? "dual" : "single",
254 ((ch_conf >> 16) & 1) ? "" : ", selected");
255 debug(" DIMMB %d MB width x%d %s rank%s\n",
256 ((ch_conf >> 8) & 0xff) * 256,
257 ((ch_conf >> 20) & 1) ? 16 : 8,
258 ((ch_conf >> 18) & 1) ? "dual" : "single",
259 ((ch_conf >> 16) & 1) ? ", selected" : "");
263 static void post_system_agent_init(struct pei_data *pei_data)
265 /* If PCIe init is skipped, set the PEG clock gating */
266 if (!pei_data->pcie_init)
267 setbits_le32(MCHBAR_REG(0x7010), 1);
270 static asmlinkage void console_tx_byte(unsigned char byte)
277 static int recovery_mode_enabled(void)
283 * Find the PEI executable in the ROM and execute it.
285 * @param pei_data: configuration data for UEFI PEI reference code
287 int sdram_initialise(struct pei_data *pei_data)
294 report_platform_info();
296 /* Wait for ME to be ready */
297 ret = intel_early_me_init();
300 ret = intel_early_me_uma_size();
304 debug("Starting UEFI PEI System Agent\n");
307 * Do not pass MRC data in for recovery mode boot,
308 * Always pass it in for S3 resume.
310 if (!recovery_mode_enabled() ||
311 pei_data->boot_mode == PEI_BOOT_RESUME) {
312 ret = prepare_mrc_cache(pei_data);
314 debug("prepare_mrc_cache failed: %d\n", ret);
317 /* If MRC data is not found we cannot continue S3 resume. */
318 if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
319 debug("Giving up in sdram_initialize: No MRC data\n");
323 /* Pass console handler in pei_data */
324 pei_data->tx_byte = console_tx_byte;
326 debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));
328 data = (char *)CONFIG_X86_MRC_ADDR;
331 int (*func)(struct pei_data *);
333 debug("Calling MRC at %p\n", data);
334 post_code(POST_PRE_MRC);
335 func = (int (*)(struct pei_data *))data;
341 printf("PEI version mismatch.\n");
344 printf("Invalid memory frequency.\n");
347 printf("MRC returned %x.\n", rv);
349 printf("Nonzero MRC return value.\n");
353 printf("UEFI PEI System Agent not found.\n");
358 /* mrc.bin reconfigures USB, so reinit it to have debug */
359 early_usbdebug_init();
362 version = readl(MCHBAR_REG(0x5034));
363 debug("System Agent Version %d.%d.%d Build %d\n",
364 version >> 24 , (version >> 16) & 0xff,
365 (version >> 8) & 0xff, version & 0xff);
366 debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len,
367 pei_data->mrc_output);
370 * Send ME init done for SandyBridge here. This is done inside the
371 * SystemAgent binary on IvyBridge
373 done = x86_pci_read_config32(PCH_DEV, PCI_DEVICE_ID);
374 done &= BASE_REV_MASK;
375 if (BASE_REV_SNB == done)
376 intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
378 intel_early_me_status();
380 post_system_agent_init(pei_data);
381 report_memory_config();
383 /* S3 resume: don't save scrambler seed or MRC data */
384 if (pei_data->boot_mode != PEI_BOOT_RESUME) {
386 * This will be copied to SDRAM in reserve_arch(), then written
387 * to SPI flash in mrccache_save()
389 gd->arch.mrc_output = (char *)pei_data->mrc_output;
390 gd->arch.mrc_output_len = pei_data->mrc_output_len;
391 ret = write_seeds_to_cmos(pei_data);
393 debug("Failed to write seeds to CMOS: %d\n", ret);
399 int reserve_arch(void)
401 return mrccache_reserve();
404 static int copy_spd(struct pei_data *peid)
406 const int gpio_vector[] = {41, 42, 43, 10, -1};
408 const void *blob = gd->fdt_blob;
413 if (gpio_vector[i] == -1)
415 ret = gpio_requestf(gpio_vector[i], "spd_id%d", i);
417 debug("%s: Could not request gpio %d\n", __func__,
422 spd_index = gpio_get_values_as_int(gpio_vector);
423 debug("spd index %d\n", spd_index);
424 node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD);
426 printf("SPD data not found.\n");
430 for (spd_node = fdt_first_subnode(blob, node);
432 spd_node = fdt_next_subnode(blob, spd_node)) {
436 if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index)
438 data = fdt_getprop(blob, spd_node, "data", &len);
439 if (len < sizeof(peid->spd_data[0])) {
440 printf("Missing SPD data\n");
444 debug("Using SDRAM SPD data for '%s'\n",
445 fdt_get_name(blob, spd_node, NULL));
446 memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
451 printf("No SPD data found for index %d\n", spd_index);
459 * add_memory_area() - Add a new usable memory area to our list
461 * Note: @start and @end must not span the first 4GB boundary
463 * @info: Place to store memory info
464 * @start: Start of this memory area
465 * @end: End of this memory area + 1
467 static int add_memory_area(struct memory_info *info,
468 uint64_t start, uint64_t end)
470 struct memory_area *ptr;
472 if (info->num_areas == CONFIG_NR_DRAM_BANKS)
475 ptr = &info->area[info->num_areas];
477 ptr->size = end - start;
478 info->total_memory += ptr->size;
479 if (ptr->start < (1ULL << 32))
480 info->total_32bit_memory += ptr->size;
481 debug("%d: memory %llx size %llx, total now %llx / %llx\n",
482 info->num_areas, ptr->start, ptr->size,
483 info->total_32bit_memory, info->total_memory);
490 * sdram_find() - Find available memory
492 * This is a bit complicated since on x86 there are system memory holes all
493 * over the place. We create a list of available memory blocks
495 static int sdram_find(pci_dev_t dev)
497 struct memory_info *info = &gd->arch.meminfo;
498 uint32_t tseg_base, uma_size, tolud;
499 uint64_t tom, me_base, touud;
500 uint64_t uma_memory_base = 0;
501 uint64_t uma_memory_size;
502 unsigned long long tomk;
505 /* Total Memory 2GB example:
507 * 00000000 0000MB-1992MB 1992MB RAM (writeback)
508 * 7c800000 1992MB-2000MB 8MB TSEG (SMRR)
509 * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached)
510 * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached)
511 * 7f200000 2034MB TOLUD
512 * 7f800000 2040MB MEBASE
513 * 7f800000 2040MB-2048MB 8MB ME UMA (uncached)
514 * 80000000 2048MB TOM
515 * 100000000 4096MB-4102MB 6MB RAM (writeback)
517 * Total Memory 4GB example:
519 * 00000000 0000MB-2768MB 2768MB RAM (writeback)
520 * ad000000 2768MB-2776MB 8MB TSEG (SMRR)
521 * ad800000 2776MB-2778MB 2MB GFX GTT (uncached)
522 * ada00000 2778MB-2810MB 32MB GFX UMA (uncached)
523 * afa00000 2810MB TOLUD
524 * ff800000 4088MB MEBASE
525 * ff800000 4088MB-4096MB 8MB ME UMA (uncached)
526 * 100000000 4096MB TOM
527 * 100000000 4096MB-5374MB 1278MB RAM (writeback)
528 * 14fe00000 5368MB TOUUD
531 /* Top of Upper Usable DRAM, including remap */
532 touud = x86_pci_read_config32(dev, TOUUD+4);
534 touud |= x86_pci_read_config32(dev, TOUUD);
536 /* Top of Lower Usable DRAM */
537 tolud = x86_pci_read_config32(dev, TOLUD);
539 /* Top of Memory - does not account for any UMA */
540 tom = x86_pci_read_config32(dev, 0xa4);
542 tom |= x86_pci_read_config32(dev, 0xa0);
544 debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom);
546 /* ME UMA needs excluding if total memory <4GB */
547 me_base = x86_pci_read_config32(dev, 0x74);
549 me_base |= x86_pci_read_config32(dev, 0x70);
551 debug("MEBASE %llx\n", me_base);
553 /* TODO: Get rid of all this shifting by 10 bits */
555 if (me_base == tolud) {
556 /* ME is from MEBASE-TOM */
557 uma_size = (tom - me_base) >> 10;
558 /* Increment TOLUD to account for ME as RAM */
559 tolud += uma_size << 10;
560 /* UMA starts at old TOLUD */
561 uma_memory_base = tomk * 1024ULL;
562 uma_memory_size = uma_size * 1024ULL;
563 debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10);
566 /* Graphics memory comes next */
567 ggc = x86_pci_read_config16(dev, GGC);
569 debug("IGD decoded, subtracting ");
571 /* Graphics memory */
572 uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL;
573 debug("%uM UMA", uma_size >> 10);
575 uma_memory_base = tomk * 1024ULL;
576 uma_memory_size += uma_size * 1024ULL;
578 /* GTT Graphics Stolen Memory Size (GGMS) */
579 uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
581 uma_memory_base = tomk * 1024ULL;
582 uma_memory_size += uma_size * 1024ULL;
583 debug(" and %uM GTT\n", uma_size >> 10);
586 /* Calculate TSEG size from its base which must be below GTT */
587 tseg_base = x86_pci_read_config32(dev, 0xb8);
588 uma_size = (uma_memory_base - tseg_base) >> 10;
590 uma_memory_base = tomk * 1024ULL;
591 uma_memory_size += uma_size * 1024ULL;
592 debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10);
594 debug("Available memory below 4GB: %lluM\n", tomk >> 10);
596 /* Report the memory regions */
597 add_memory_area(info, 1 << 20, 2 << 28);
598 add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
599 add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
600 add_memory_area(info, 1ULL << 32, touud);
602 /* Add MTRRs for memory */
603 mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
604 mtrr_add_request(MTRR_TYPE_WRBACK, 2ULL << 30, 512 << 20);
605 mtrr_add_request(MTRR_TYPE_WRBACK, 0xaULL << 28, 256 << 20);
606 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base, 16 << 20);
607 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base + (16 << 20),
611 * If >= 4GB installed then memory from TOLUD to 4GB
612 * is remapped above TOM, TOUUD will account for both
614 if (touud > (1ULL << 32ULL)) {
615 debug("Available memory above 4GB: %lluM\n",
616 (touud >> 20) - 4096);
622 static void rcba_config(void)
625 * GFX INTA -> PIRQA (MSI)
626 * D28IP_P3IP WLAN INTA -> PIRQB
627 * D29IP_E1P EHCI1 INTA -> PIRQD
628 * D26IP_E2P EHCI2 INTA -> PIRQF
629 * D31IP_SIP SATA INTA -> PIRQF (MSI)
630 * D31IP_SMIP SMBUS INTB -> PIRQH
631 * D31IP_TTIP THRT INTC -> PIRQA
632 * D27IP_ZIP HDA INTA -> PIRQA (MSI)
634 * TRACKPAD -> PIRQE (Edge Triggered)
635 * TOUCHSCREEN -> PIRQG (Edge Triggered)
638 /* Device interrupt pin register (board specific) */
639 writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
640 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP));
641 writel(NOINT << D30IP_PIP, RCB_REG(D30IP));
642 writel(INTA << D29IP_E1P, RCB_REG(D29IP));
643 writel(INTA << D28IP_P3IP, RCB_REG(D28IP));
644 writel(INTA << D27IP_ZIP, RCB_REG(D27IP));
645 writel(INTA << D26IP_E2P, RCB_REG(D26IP));
646 writel(NOINT << D25IP_LIP, RCB_REG(D25IP));
647 writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP));
649 /* Device interrupt route registers */
650 writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR));
651 writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR));
652 writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR));
653 writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR));
654 writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR));
655 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR));
656 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR));
658 /* Enable IOAPIC (generic) */
659 writew(0x0100, RCB_REG(OIC));
660 /* PCH BWG says to read back the IOAPIC enable register */
661 (void)readw(RCB_REG(OIC));
663 /* Disable unused devices (board specific) */
664 setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS);
669 struct pei_data pei_data __aligned(8) = {
670 .pei_version = PEI_VERSION,
671 .mchbar = DEFAULT_MCHBAR,
672 .dmibar = DEFAULT_DMIBAR,
673 .epbar = DEFAULT_EPBAR,
674 .pciexbar = CONFIG_PCIE_ECAM_BASE,
675 .smbusbar = SMBUS_IO_BASE,
678 .hpet_address = CONFIG_HPET_ADDRESS,
679 .rcba = DEFAULT_RCBABASE,
680 .pmbase = DEFAULT_PMBASE,
681 .gpiobase = DEFAULT_GPIOBASE,
682 .thermalbase = 0xfed08000,
683 .system_type = 0, /* 0 Mobile, 1 Desktop/Server */
684 .tseg_size = CONFIG_SMM_TSEG_SIZE,
685 .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
689 * 0 = leave channel enabled
690 * 1 = disable dimm 0 on channel
691 * 2 = disable dimm 1 on channel
692 * 3 = disable dimm 0+1 on channel
694 .dimm_channel0_disabled = 2,
695 .dimm_channel1_disabled = 2,
696 .max_ddr3_freq = 1600,
699 * Empty and onboard Ports 0-7, set to un-used pin
702 { 0, 3, 0x0000 }, /* P0= Empty */
703 { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */
704 { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */
705 { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */
706 { 0, 3, 0x0000 }, /* P4= Empty */
707 { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */
708 { 0, 3, 0x0000 }, /* P6= Empty */
709 { 0, 3, 0x0000 }, /* P7= Empty */
711 * Empty and onboard Ports 8-13, set to un-used pin
714 { 1, 4, 0x0040 }, /* P8= Camera (no OC) */
715 { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */
716 { 0, 4, 0x0000 }, /* P10= Empty */
717 { 0, 4, 0x0000 }, /* P11= Empty */
718 { 0, 4, 0x0000 }, /* P12= Empty */
719 { 0, 4, 0x0000 }, /* P13= Empty */
722 pci_dev_t dev = PCI_BDF(0, 0, 0);
725 debug("Boot mode %d\n", gd->arch.pei_boot_mode);
726 debug("mrc_input %p\n", pei_data.mrc_input);
727 pei_data.boot_mode = gd->arch.pei_boot_mode;
728 ret = copy_spd(&pei_data);
730 ret = sdram_initialise(&pei_data);
737 writew(0xCAFE, MCHBAR_REG(SSKPD));
739 post_code(POST_DRAM);
741 ret = sdram_find(dev);
745 gd->ram_size = gd->arch.meminfo.total_32bit_memory;