2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2010,2011
4 * Graeme Russ, <graeme.russ@gmail.com>
6 * Portions from Coreboot mainboard/google/link/romstage.c
7 * Copyright (C) 2007-2010 coresystems GmbH
8 * Copyright (C) 2011 Google Inc.
10 * SPDX-License-Identifier: GPL-2.0
20 #include <spi_flash.h>
21 #include <asm/processor.h>
23 #include <asm/global_data.h>
24 #include <asm/mrccache.h>
27 #include <asm/arch/me.h>
28 #include <asm/arch/pei_data.h>
29 #include <asm/arch/pch.h>
31 #include <asm/arch/sandybridge.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 #define CMOS_OFFSET_MRC_SEED 152
36 #define CMOS_OFFSET_MRC_SEED_S3 156
37 #define CMOS_OFFSET_MRC_SEED_CHK 160
40 * This function looks for the highest region of memory lower than 4GB which
41 * has enough space for U-Boot where U-Boot is aligned on a page boundary.
42 * It overrides the default implementation found elsewhere which simply
43 * picks the end of ram, wherever that may be. The location of the stack,
44 * the relocation address, and how far U-Boot is moved by relocation are
45 * set in the global data structure.
47 ulong board_get_usable_ram_top(ulong total_size)
49 struct memory_info *info = &gd->arch.meminfo;
50 uintptr_t dest_addr = 0;
51 struct memory_area *largest = NULL;
54 /* Find largest area of memory below 4GB */
56 for (i = 0; i < info->num_areas; i++) {
57 struct memory_area *area = &info->area[i];
59 if (area->start >= 1ULL << 32)
61 if (!largest || area->size > largest->size)
65 /* If no suitable area was found, return an error. */
67 if (!largest || largest->size < (2 << 20))
68 panic("No available memory found for relocation");
70 dest_addr = largest->start + largest->size;
72 return (ulong)dest_addr;
75 void dram_init_banksize(void)
77 struct memory_info *info = &gd->arch.meminfo;
81 for (i = 0, num_banks = 0; i < info->num_areas; i++) {
82 struct memory_area *area = &info->area[i];
84 if (area->start >= 1ULL << 32)
86 gd->bd->bi_dram[num_banks].start = area->start;
87 gd->bd->bi_dram[num_banks].size = area->size;
92 static int read_seed_from_cmos(struct pei_data *pei_data)
94 u16 c1, c2, checksum, seed_checksum;
98 ret = uclass_get_device(UCLASS_RTC, 0, &dev);
100 debug("Cannot find RTC: err=%d\n", ret);
105 * Read scrambler seeds from CMOS RAM. We don't want to store them in
106 * SPI flash since they change on every boot and that would wear down
107 * the flash too much. So we store these in CMOS and the large MRC
110 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed);
112 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED_S3,
113 &pei_data->scrambler_seed_s3);
116 debug("Failed to read from RTC %s\n", dev->name);
120 debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n",
121 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
122 debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n",
123 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
125 /* Compute seed checksum and compare */
126 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed,
128 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3,
130 checksum = add_ip_checksums(sizeof(u32), c1, c2);
132 seed_checksum = rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK);
133 seed_checksum |= rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1) << 8;
135 if (checksum != seed_checksum) {
136 debug("%s: invalid seed checksum\n", __func__);
137 pei_data->scrambler_seed = 0;
138 pei_data->scrambler_seed_s3 = 0;
145 static int prepare_mrc_cache(struct pei_data *pei_data)
147 struct mrc_data_container *mrc_cache;
148 struct mrc_region entry;
151 ret = read_seed_from_cmos(pei_data);
154 ret = mrccache_get_region(NULL, &entry);
157 mrc_cache = mrccache_find_current(&entry);
161 pei_data->mrc_input = mrc_cache->data;
162 pei_data->mrc_input_len = mrc_cache->data_size;
163 debug("%s: at %p, size %x checksum %04x\n", __func__,
164 pei_data->mrc_input, pei_data->mrc_input_len,
165 mrc_cache->checksum);
170 static int write_seeds_to_cmos(struct pei_data *pei_data)
172 u16 c1, c2, checksum;
176 ret = uclass_get_device(UCLASS_RTC, 0, &dev);
178 debug("Cannot find RTC: err=%d\n", ret);
182 /* Save the MRC seed values to CMOS */
183 rtc_write32(dev, CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
184 debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n",
185 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
187 rtc_write32(dev, CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
188 debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n",
189 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
191 /* Save a simple checksum of the seed values */
192 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed,
194 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3,
196 checksum = add_ip_checksums(sizeof(u32), c1, c2);
198 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff);
199 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff);
204 /* Use this hook to save our SDRAM parameters */
205 int misc_init_r(void)
209 ret = mrccache_save();
211 printf("Unable to save MRC data: %d\n", ret);
216 static const char *const ecc_decoder[] = {
224 * Dump in the log memory controller configuration as read from the memory
225 * controller registers.
227 static void report_memory_config(void)
229 u32 addr_decoder_common, addr_decode_ch[2];
232 addr_decoder_common = readl(MCHBAR_REG(0x5000));
233 addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
234 addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
236 debug("memcfg DDR3 clock %d MHz\n",
237 (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100);
238 debug("memcfg channel assignment: A: %d, B % d, C % d\n",
239 addr_decoder_common & 3,
240 (addr_decoder_common >> 2) & 3,
241 (addr_decoder_common >> 4) & 3);
243 for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
244 u32 ch_conf = addr_decode_ch[i];
245 debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
246 debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
247 debug(" enhanced interleave mode %s\n",
248 ((ch_conf >> 22) & 1) ? "on" : "off");
249 debug(" rank interleave %s\n",
250 ((ch_conf >> 21) & 1) ? "on" : "off");
251 debug(" DIMMA %d MB width x%d %s rank%s\n",
252 ((ch_conf >> 0) & 0xff) * 256,
253 ((ch_conf >> 19) & 1) ? 16 : 8,
254 ((ch_conf >> 17) & 1) ? "dual" : "single",
255 ((ch_conf >> 16) & 1) ? "" : ", selected");
256 debug(" DIMMB %d MB width x%d %s rank%s\n",
257 ((ch_conf >> 8) & 0xff) * 256,
258 ((ch_conf >> 20) & 1) ? 16 : 8,
259 ((ch_conf >> 18) & 1) ? "dual" : "single",
260 ((ch_conf >> 16) & 1) ? ", selected" : "");
264 static void post_system_agent_init(struct pei_data *pei_data)
266 /* If PCIe init is skipped, set the PEG clock gating */
267 if (!pei_data->pcie_init)
268 setbits_le32(MCHBAR_REG(0x7010), 1);
271 static asmlinkage void console_tx_byte(unsigned char byte)
278 static int recovery_mode_enabled(void)
284 * Find the PEI executable in the ROM and execute it.
286 * @dev: Northbridge device
287 * @pei_data: configuration data for UEFI PEI reference code
289 int sdram_initialise(struct udevice *dev, struct pei_data *pei_data)
296 report_platform_info();
298 /* Wait for ME to be ready */
299 ret = intel_early_me_init();
302 ret = intel_early_me_uma_size();
306 debug("Starting UEFI PEI System Agent\n");
309 * Do not pass MRC data in for recovery mode boot,
310 * Always pass it in for S3 resume.
312 if (!recovery_mode_enabled() ||
313 pei_data->boot_mode == PEI_BOOT_RESUME) {
314 ret = prepare_mrc_cache(pei_data);
316 debug("prepare_mrc_cache failed: %d\n", ret);
319 /* If MRC data is not found we cannot continue S3 resume. */
320 if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
321 debug("Giving up in sdram_initialize: No MRC data\n");
325 /* Pass console handler in pei_data */
326 pei_data->tx_byte = console_tx_byte;
328 debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));
330 data = (char *)CONFIG_X86_MRC_ADDR;
333 int (*func)(struct pei_data *);
336 debug("Calling MRC at %p\n", data);
337 post_code(POST_PRE_MRC);
338 start = get_timer(0);
339 func = (int (*)(struct pei_data *))data;
345 printf("PEI version mismatch.\n");
348 printf("Invalid memory frequency.\n");
351 printf("MRC returned %x.\n", rv);
353 printf("Nonzero MRC return value.\n");
356 debug("MRC execution time %lu ms\n", get_timer(start));
358 printf("UEFI PEI System Agent not found.\n");
363 /* mrc.bin reconfigures USB, so reinit it to have debug */
364 early_usbdebug_init();
367 version = readl(MCHBAR_REG(0x5034));
368 debug("System Agent Version %d.%d.%d Build %d\n",
369 version >> 24 , (version >> 16) & 0xff,
370 (version >> 8) & 0xff, version & 0xff);
371 debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len,
372 pei_data->mrc_output);
375 * Send ME init done for SandyBridge here. This is done inside the
376 * SystemAgent binary on IvyBridge
378 dm_pci_read_config16(dev, PCI_DEVICE_ID, &done);
379 done &= BASE_REV_MASK;
380 if (BASE_REV_SNB == done)
381 intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
383 intel_early_me_status();
385 post_system_agent_init(pei_data);
386 report_memory_config();
388 /* S3 resume: don't save scrambler seed or MRC data */
389 if (pei_data->boot_mode != PEI_BOOT_RESUME) {
391 * This will be copied to SDRAM in reserve_arch(), then written
392 * to SPI flash in mrccache_save()
394 gd->arch.mrc_output = (char *)pei_data->mrc_output;
395 gd->arch.mrc_output_len = pei_data->mrc_output_len;
396 ret = write_seeds_to_cmos(pei_data);
398 debug("Failed to write seeds to CMOS: %d\n", ret);
404 int reserve_arch(void)
406 return mrccache_reserve();
409 static int copy_spd(struct pei_data *peid)
411 const int gpio_vector[] = {41, 42, 43, 10, -1};
413 const void *blob = gd->fdt_blob;
418 if (gpio_vector[i] == -1)
420 ret = gpio_requestf(gpio_vector[i], "spd_id%d", i);
422 debug("%s: Could not request gpio %d\n", __func__,
427 spd_index = gpio_get_values_as_int(gpio_vector);
428 debug("spd index %d\n", spd_index);
429 node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD);
431 printf("SPD data not found.\n");
435 for (spd_node = fdt_first_subnode(blob, node);
437 spd_node = fdt_next_subnode(blob, spd_node)) {
441 if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index)
443 data = fdt_getprop(blob, spd_node, "data", &len);
444 if (len < sizeof(peid->spd_data[0])) {
445 printf("Missing SPD data\n");
449 debug("Using SDRAM SPD data for '%s'\n",
450 fdt_get_name(blob, spd_node, NULL));
451 memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
456 printf("No SPD data found for index %d\n", spd_index);
464 * add_memory_area() - Add a new usable memory area to our list
466 * Note: @start and @end must not span the first 4GB boundary
468 * @info: Place to store memory info
469 * @start: Start of this memory area
470 * @end: End of this memory area + 1
472 static int add_memory_area(struct memory_info *info,
473 uint64_t start, uint64_t end)
475 struct memory_area *ptr;
477 if (info->num_areas == CONFIG_NR_DRAM_BANKS)
480 ptr = &info->area[info->num_areas];
482 ptr->size = end - start;
483 info->total_memory += ptr->size;
484 if (ptr->start < (1ULL << 32))
485 info->total_32bit_memory += ptr->size;
486 debug("%d: memory %llx size %llx, total now %llx / %llx\n",
487 info->num_areas, ptr->start, ptr->size,
488 info->total_32bit_memory, info->total_memory);
495 * sdram_find() - Find available memory
497 * This is a bit complicated since on x86 there are system memory holes all
498 * over the place. We create a list of available memory blocks
500 * @dev: Northbridge device
502 static int sdram_find(struct udevice *dev)
504 struct memory_info *info = &gd->arch.meminfo;
505 uint32_t tseg_base, uma_size, tolud;
506 uint64_t tom, me_base, touud;
507 uint64_t uma_memory_base = 0;
508 uint64_t uma_memory_size;
509 unsigned long long tomk;
513 /* Total Memory 2GB example:
515 * 00000000 0000MB-1992MB 1992MB RAM (writeback)
516 * 7c800000 1992MB-2000MB 8MB TSEG (SMRR)
517 * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached)
518 * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached)
519 * 7f200000 2034MB TOLUD
520 * 7f800000 2040MB MEBASE
521 * 7f800000 2040MB-2048MB 8MB ME UMA (uncached)
522 * 80000000 2048MB TOM
523 * 100000000 4096MB-4102MB 6MB RAM (writeback)
525 * Total Memory 4GB example:
527 * 00000000 0000MB-2768MB 2768MB RAM (writeback)
528 * ad000000 2768MB-2776MB 8MB TSEG (SMRR)
529 * ad800000 2776MB-2778MB 2MB GFX GTT (uncached)
530 * ada00000 2778MB-2810MB 32MB GFX UMA (uncached)
531 * afa00000 2810MB TOLUD
532 * ff800000 4088MB MEBASE
533 * ff800000 4088MB-4096MB 8MB ME UMA (uncached)
534 * 100000000 4096MB TOM
535 * 100000000 4096MB-5374MB 1278MB RAM (writeback)
536 * 14fe00000 5368MB TOUUD
539 /* Top of Upper Usable DRAM, including remap */
540 dm_pci_read_config32(dev, TOUUD + 4, &val);
541 touud = (uint64_t)val << 32;
542 dm_pci_read_config32(dev, TOUUD, &val);
545 /* Top of Lower Usable DRAM */
546 dm_pci_read_config32(dev, TOLUD, &tolud);
548 /* Top of Memory - does not account for any UMA */
549 dm_pci_read_config32(dev, 0xa4, &val);
550 tom = (uint64_t)val << 32;
551 dm_pci_read_config32(dev, 0xa0, &val);
554 debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom);
556 /* ME UMA needs excluding if total memory <4GB */
557 dm_pci_read_config32(dev, 0x74, &val);
558 me_base = (uint64_t)val << 32;
559 dm_pci_read_config32(dev, 0x70, &val);
562 debug("MEBASE %llx\n", me_base);
564 /* TODO: Get rid of all this shifting by 10 bits */
566 if (me_base == tolud) {
567 /* ME is from MEBASE-TOM */
568 uma_size = (tom - me_base) >> 10;
569 /* Increment TOLUD to account for ME as RAM */
570 tolud += uma_size << 10;
571 /* UMA starts at old TOLUD */
572 uma_memory_base = tomk * 1024ULL;
573 uma_memory_size = uma_size * 1024ULL;
574 debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10);
577 /* Graphics memory comes next */
578 dm_pci_read_config16(dev, GGC, &ggc);
580 debug("IGD decoded, subtracting ");
582 /* Graphics memory */
583 uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL;
584 debug("%uM UMA", uma_size >> 10);
586 uma_memory_base = tomk * 1024ULL;
587 uma_memory_size += uma_size * 1024ULL;
589 /* GTT Graphics Stolen Memory Size (GGMS) */
590 uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
592 uma_memory_base = tomk * 1024ULL;
593 uma_memory_size += uma_size * 1024ULL;
594 debug(" and %uM GTT\n", uma_size >> 10);
597 /* Calculate TSEG size from its base which must be below GTT */
598 dm_pci_read_config32(dev, 0xb8, &tseg_base);
599 uma_size = (uma_memory_base - tseg_base) >> 10;
601 uma_memory_base = tomk * 1024ULL;
602 uma_memory_size += uma_size * 1024ULL;
603 debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10);
605 debug("Available memory below 4GB: %lluM\n", tomk >> 10);
607 /* Report the memory regions */
608 add_memory_area(info, 1 << 20, 2 << 28);
609 add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
610 add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
611 add_memory_area(info, 1ULL << 32, touud);
613 /* Add MTRRs for memory */
614 mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
615 mtrr_add_request(MTRR_TYPE_WRBACK, 2ULL << 30, 512 << 20);
616 mtrr_add_request(MTRR_TYPE_WRBACK, 0xaULL << 28, 256 << 20);
617 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base, 16 << 20);
618 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base + (16 << 20),
622 * If >= 4GB installed then memory from TOLUD to 4GB
623 * is remapped above TOM, TOUUD will account for both
625 if (touud > (1ULL << 32ULL)) {
626 debug("Available memory above 4GB: %lluM\n",
627 (touud >> 20) - 4096);
633 static void rcba_config(void)
636 * GFX INTA -> PIRQA (MSI)
637 * D28IP_P3IP WLAN INTA -> PIRQB
638 * D29IP_E1P EHCI1 INTA -> PIRQD
639 * D26IP_E2P EHCI2 INTA -> PIRQF
640 * D31IP_SIP SATA INTA -> PIRQF (MSI)
641 * D31IP_SMIP SMBUS INTB -> PIRQH
642 * D31IP_TTIP THRT INTC -> PIRQA
643 * D27IP_ZIP HDA INTA -> PIRQA (MSI)
645 * TRACKPAD -> PIRQE (Edge Triggered)
646 * TOUCHSCREEN -> PIRQG (Edge Triggered)
649 /* Device interrupt pin register (board specific) */
650 writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
651 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP));
652 writel(NOINT << D30IP_PIP, RCB_REG(D30IP));
653 writel(INTA << D29IP_E1P, RCB_REG(D29IP));
654 writel(INTA << D28IP_P3IP, RCB_REG(D28IP));
655 writel(INTA << D27IP_ZIP, RCB_REG(D27IP));
656 writel(INTA << D26IP_E2P, RCB_REG(D26IP));
657 writel(NOINT << D25IP_LIP, RCB_REG(D25IP));
658 writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP));
660 /* Device interrupt route registers */
661 writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR));
662 writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR));
663 writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR));
664 writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR));
665 writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR));
666 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR));
667 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR));
669 /* Enable IOAPIC (generic) */
670 writew(0x0100, RCB_REG(OIC));
671 /* PCH BWG says to read back the IOAPIC enable register */
672 (void)readw(RCB_REG(OIC));
674 /* Disable unused devices (board specific) */
675 setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS);
680 struct pei_data pei_data __aligned(8) = {
681 .pei_version = PEI_VERSION,
682 .mchbar = DEFAULT_MCHBAR,
683 .dmibar = DEFAULT_DMIBAR,
684 .epbar = DEFAULT_EPBAR,
685 .pciexbar = CONFIG_PCIE_ECAM_BASE,
686 .smbusbar = SMBUS_IO_BASE,
689 .hpet_address = CONFIG_HPET_ADDRESS,
690 .rcba = DEFAULT_RCBABASE,
691 .pmbase = DEFAULT_PMBASE,
692 .gpiobase = DEFAULT_GPIOBASE,
693 .thermalbase = 0xfed08000,
694 .system_type = 0, /* 0 Mobile, 1 Desktop/Server */
695 .tseg_size = CONFIG_SMM_TSEG_SIZE,
696 .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
700 * 0 = leave channel enabled
701 * 1 = disable dimm 0 on channel
702 * 2 = disable dimm 1 on channel
703 * 3 = disable dimm 0+1 on channel
705 .dimm_channel0_disabled = 2,
706 .dimm_channel1_disabled = 2,
707 .max_ddr3_freq = 1600,
710 * Empty and onboard Ports 0-7, set to un-used pin
713 { 0, 3, 0x0000 }, /* P0= Empty */
714 { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */
715 { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */
716 { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */
717 { 0, 3, 0x0000 }, /* P4= Empty */
718 { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */
719 { 0, 3, 0x0000 }, /* P6= Empty */
720 { 0, 3, 0x0000 }, /* P7= Empty */
722 * Empty and onboard Ports 8-13, set to un-used pin
725 { 1, 4, 0x0040 }, /* P8= Camera (no OC) */
726 { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */
727 { 0, 4, 0x0000 }, /* P10= Empty */
728 { 0, 4, 0x0000 }, /* P11= Empty */
729 { 0, 4, 0x0000 }, /* P12= Empty */
730 { 0, 4, 0x0000 }, /* P13= Empty */
736 ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
741 debug("Boot mode %d\n", gd->arch.pei_boot_mode);
742 debug("mrc_input %p\n", pei_data.mrc_input);
743 pei_data.boot_mode = gd->arch.pei_boot_mode;
744 ret = copy_spd(&pei_data);
746 ret = sdram_initialise(dev, &pei_data);
753 writew(0xCAFE, MCHBAR_REG(SSKPD));
755 post_code(POST_DRAM);
757 ret = sdram_find(dev);
761 gd->ram_size = gd->arch.meminfo.total_32bit_memory;