2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2010,2011
4 * Graeme Russ, <graeme.russ@gmail.com>
6 * Portions from Coreboot mainboard/google/link/romstage.c
7 * Copyright (C) 2007-2010 coresystems GmbH
8 * Copyright (C) 2011 Google Inc.
10 * SPDX-License-Identifier: GPL-2.0
20 #include <spi_flash.h>
23 #include <asm/processor.h>
25 #include <asm/global_data.h>
26 #include <asm/intel_regs.h>
27 #include <asm/mrccache.h>
28 #include <asm/mrc_common.h>
31 #include <asm/report_platform.h>
32 #include <asm/arch/me.h>
33 #include <asm/arch/pei_data.h>
34 #include <asm/arch/pch.h>
36 #include <asm/arch/sandybridge.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 #define CMOS_OFFSET_MRC_SEED 152
41 #define CMOS_OFFSET_MRC_SEED_S3 156
42 #define CMOS_OFFSET_MRC_SEED_CHK 160
44 ulong board_get_usable_ram_top(ulong total_size)
46 return mrc_common_board_get_usable_ram_top(total_size);
49 void dram_init_banksize(void)
51 mrc_common_dram_init_banksize();
54 static int read_seed_from_cmos(struct pei_data *pei_data)
56 u16 c1, c2, checksum, seed_checksum;
60 ret = uclass_get_device(UCLASS_RTC, 0, &dev);
62 debug("Cannot find RTC: err=%d\n", ret);
67 * Read scrambler seeds from CMOS RAM. We don't want to store them in
68 * SPI flash since they change on every boot and that would wear down
69 * the flash too much. So we store these in CMOS and the large MRC
72 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed);
74 ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED_S3,
75 &pei_data->scrambler_seed_s3);
78 debug("Failed to read from RTC %s\n", dev->name);
82 debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n",
83 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
84 debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n",
85 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
87 /* Compute seed checksum and compare */
88 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed,
90 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3,
92 checksum = add_ip_checksums(sizeof(u32), c1, c2);
94 seed_checksum = rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK);
95 seed_checksum |= rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1) << 8;
97 if (checksum != seed_checksum) {
98 debug("%s: invalid seed checksum\n", __func__);
99 pei_data->scrambler_seed = 0;
100 pei_data->scrambler_seed_s3 = 0;
107 static int prepare_mrc_cache(struct pei_data *pei_data)
109 struct mrc_data_container *mrc_cache;
110 struct mrc_region entry;
113 ret = read_seed_from_cmos(pei_data);
116 ret = mrccache_get_region(NULL, &entry);
119 mrc_cache = mrccache_find_current(&entry);
123 pei_data->mrc_input = mrc_cache->data;
124 pei_data->mrc_input_len = mrc_cache->data_size;
125 debug("%s: at %p, size %x checksum %04x\n", __func__,
126 pei_data->mrc_input, pei_data->mrc_input_len,
127 mrc_cache->checksum);
132 static int write_seeds_to_cmos(struct pei_data *pei_data)
134 u16 c1, c2, checksum;
138 ret = uclass_get_device(UCLASS_RTC, 0, &dev);
140 debug("Cannot find RTC: err=%d\n", ret);
144 /* Save the MRC seed values to CMOS */
145 rtc_write32(dev, CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
146 debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n",
147 pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
149 rtc_write32(dev, CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
150 debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n",
151 pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
153 /* Save a simple checksum of the seed values */
154 c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed,
156 c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3,
158 checksum = add_ip_checksums(sizeof(u32), c1, c2);
160 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff);
161 rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff);
166 /* Use this hook to save our SDRAM parameters */
167 int misc_init_r(void)
171 ret = mrccache_save();
173 printf("Unable to save MRC data: %d\n", ret);
178 static void post_system_agent_init(struct udevice *dev, struct udevice *me_dev,
179 struct pei_data *pei_data)
184 * Send ME init done for SandyBridge here. This is done inside the
185 * SystemAgent binary on IvyBridge
187 dm_pci_read_config16(dev, PCI_DEVICE_ID, &done);
188 done &= BASE_REV_MASK;
189 if (BASE_REV_SNB == done)
190 intel_early_me_init_done(dev, me_dev, ME_INIT_STATUS_SUCCESS);
192 intel_me_status(me_dev);
194 /* If PCIe init is skipped, set the PEG clock gating */
195 if (!pei_data->pcie_init)
196 setbits_le32(MCHBAR_REG(0x7010), 1);
199 static int recovery_mode_enabled(void)
204 int reserve_arch(void)
206 return mrccache_reserve();
209 static int copy_spd(struct udevice *dev, struct pei_data *peid)
214 ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), &data);
218 memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
224 * sdram_find() - Find available memory
226 * This is a bit complicated since on x86 there are system memory holes all
227 * over the place. We create a list of available memory blocks
229 * @dev: Northbridge device
231 static int sdram_find(struct udevice *dev)
233 struct memory_info *info = &gd->arch.meminfo;
234 uint32_t tseg_base, uma_size, tolud;
235 uint64_t tom, me_base, touud;
236 uint64_t uma_memory_base = 0;
237 uint64_t uma_memory_size;
238 unsigned long long tomk;
242 /* Total Memory 2GB example:
244 * 00000000 0000MB-1992MB 1992MB RAM (writeback)
245 * 7c800000 1992MB-2000MB 8MB TSEG (SMRR)
246 * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached)
247 * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached)
248 * 7f200000 2034MB TOLUD
249 * 7f800000 2040MB MEBASE
250 * 7f800000 2040MB-2048MB 8MB ME UMA (uncached)
251 * 80000000 2048MB TOM
252 * 100000000 4096MB-4102MB 6MB RAM (writeback)
254 * Total Memory 4GB example:
256 * 00000000 0000MB-2768MB 2768MB RAM (writeback)
257 * ad000000 2768MB-2776MB 8MB TSEG (SMRR)
258 * ad800000 2776MB-2778MB 2MB GFX GTT (uncached)
259 * ada00000 2778MB-2810MB 32MB GFX UMA (uncached)
260 * afa00000 2810MB TOLUD
261 * ff800000 4088MB MEBASE
262 * ff800000 4088MB-4096MB 8MB ME UMA (uncached)
263 * 100000000 4096MB TOM
264 * 100000000 4096MB-5374MB 1278MB RAM (writeback)
265 * 14fe00000 5368MB TOUUD
268 /* Top of Upper Usable DRAM, including remap */
269 dm_pci_read_config32(dev, TOUUD + 4, &val);
270 touud = (uint64_t)val << 32;
271 dm_pci_read_config32(dev, TOUUD, &val);
274 /* Top of Lower Usable DRAM */
275 dm_pci_read_config32(dev, TOLUD, &tolud);
277 /* Top of Memory - does not account for any UMA */
278 dm_pci_read_config32(dev, 0xa4, &val);
279 tom = (uint64_t)val << 32;
280 dm_pci_read_config32(dev, 0xa0, &val);
283 debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom);
285 /* ME UMA needs excluding if total memory <4GB */
286 dm_pci_read_config32(dev, 0x74, &val);
287 me_base = (uint64_t)val << 32;
288 dm_pci_read_config32(dev, 0x70, &val);
291 debug("MEBASE %llx\n", me_base);
293 /* TODO: Get rid of all this shifting by 10 bits */
295 if (me_base == tolud) {
296 /* ME is from MEBASE-TOM */
297 uma_size = (tom - me_base) >> 10;
298 /* Increment TOLUD to account for ME as RAM */
299 tolud += uma_size << 10;
300 /* UMA starts at old TOLUD */
301 uma_memory_base = tomk * 1024ULL;
302 uma_memory_size = uma_size * 1024ULL;
303 debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10);
306 /* Graphics memory comes next */
307 dm_pci_read_config16(dev, GGC, &ggc);
309 debug("IGD decoded, subtracting ");
311 /* Graphics memory */
312 uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL;
313 debug("%uM UMA", uma_size >> 10);
315 uma_memory_base = tomk * 1024ULL;
316 uma_memory_size += uma_size * 1024ULL;
318 /* GTT Graphics Stolen Memory Size (GGMS) */
319 uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
321 uma_memory_base = tomk * 1024ULL;
322 uma_memory_size += uma_size * 1024ULL;
323 debug(" and %uM GTT\n", uma_size >> 10);
326 /* Calculate TSEG size from its base which must be below GTT */
327 dm_pci_read_config32(dev, 0xb8, &tseg_base);
328 uma_size = (uma_memory_base - tseg_base) >> 10;
330 uma_memory_base = tomk * 1024ULL;
331 uma_memory_size += uma_size * 1024ULL;
332 debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10);
334 debug("Available memory below 4GB: %lluM\n", tomk >> 10);
336 /* Report the memory regions */
337 mrc_add_memory_area(info, 1 << 20, 2 << 28);
338 mrc_add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
339 mrc_add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
340 mrc_add_memory_area(info, 1ULL << 32, touud);
342 /* Add MTRRs for memory */
343 mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
344 mtrr_add_request(MTRR_TYPE_WRBACK, 2ULL << 30, 512 << 20);
345 mtrr_add_request(MTRR_TYPE_WRBACK, 0xaULL << 28, 256 << 20);
346 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base, 16 << 20);
347 mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base + (16 << 20),
351 * If >= 4GB installed then memory from TOLUD to 4GB
352 * is remapped above TOM, TOUUD will account for both
354 if (touud > (1ULL << 32ULL)) {
355 debug("Available memory above 4GB: %lluM\n",
356 (touud >> 20) - 4096);
362 static void rcba_config(void)
365 * GFX INTA -> PIRQA (MSI)
366 * D28IP_P3IP WLAN INTA -> PIRQB
367 * D29IP_E1P EHCI1 INTA -> PIRQD
368 * D26IP_E2P EHCI2 INTA -> PIRQF
369 * D31IP_SIP SATA INTA -> PIRQF (MSI)
370 * D31IP_SMIP SMBUS INTB -> PIRQH
371 * D31IP_TTIP THRT INTC -> PIRQA
372 * D27IP_ZIP HDA INTA -> PIRQA (MSI)
374 * TRACKPAD -> PIRQE (Edge Triggered)
375 * TOUCHSCREEN -> PIRQG (Edge Triggered)
378 /* Device interrupt pin register (board specific) */
379 writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
380 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP));
381 writel(NOINT << D30IP_PIP, RCB_REG(D30IP));
382 writel(INTA << D29IP_E1P, RCB_REG(D29IP));
383 writel(INTA << D28IP_P3IP, RCB_REG(D28IP));
384 writel(INTA << D27IP_ZIP, RCB_REG(D27IP));
385 writel(INTA << D26IP_E2P, RCB_REG(D26IP));
386 writel(NOINT << D25IP_LIP, RCB_REG(D25IP));
387 writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP));
389 /* Device interrupt route registers */
390 writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR));
391 writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR));
392 writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR));
393 writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR));
394 writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR));
395 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR));
396 writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR));
398 /* Enable IOAPIC (generic) */
399 writew(0x0100, RCB_REG(OIC));
400 /* PCH BWG says to read back the IOAPIC enable register */
401 (void)readw(RCB_REG(OIC));
403 /* Disable unused devices (board specific) */
404 setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS);
409 struct pei_data _pei_data __aligned(8) = {
410 .pei_version = PEI_VERSION,
411 .mchbar = MCH_BASE_ADDRESS,
412 .dmibar = DEFAULT_DMIBAR,
413 .epbar = DEFAULT_EPBAR,
414 .pciexbar = CONFIG_PCIE_ECAM_BASE,
415 .smbusbar = SMBUS_IO_BASE,
418 .hpet_address = CONFIG_HPET_ADDRESS,
419 .rcba = DEFAULT_RCBABASE,
420 .pmbase = DEFAULT_PMBASE,
421 .gpiobase = DEFAULT_GPIOBASE,
422 .thermalbase = 0xfed08000,
423 .system_type = 0, /* 0 Mobile, 1 Desktop/Server */
424 .tseg_size = CONFIG_SMM_TSEG_SIZE,
425 .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
429 * 0 = leave channel enabled
430 * 1 = disable dimm 0 on channel
431 * 2 = disable dimm 1 on channel
432 * 3 = disable dimm 0+1 on channel
434 .dimm_channel0_disabled = 2,
435 .dimm_channel1_disabled = 2,
436 .max_ddr3_freq = 1600,
439 * Empty and onboard Ports 0-7, set to un-used pin
442 { 0, 3, 0x0000 }, /* P0= Empty */
443 { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */
444 { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */
445 { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */
446 { 0, 3, 0x0000 }, /* P4= Empty */
447 { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */
448 { 0, 3, 0x0000 }, /* P6= Empty */
449 { 0, 3, 0x0000 }, /* P7= Empty */
451 * Empty and onboard Ports 8-13, set to un-used pin
454 { 1, 4, 0x0040 }, /* P8= Camera (no OC) */
455 { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */
456 { 0, 4, 0x0000 }, /* P10= Empty */
457 { 0, 4, 0x0000 }, /* P11= Empty */
458 { 0, 4, 0x0000 }, /* P12= Empty */
459 { 0, 4, 0x0000 }, /* P13= Empty */
462 struct pei_data *pei_data = &_pei_data;
463 struct udevice *dev, *me_dev;
466 ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
469 ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
472 ret = copy_spd(dev, pei_data);
475 pei_data->boot_mode = gd->arch.pei_boot_mode;
476 debug("Boot mode %d\n", gd->arch.pei_boot_mode);
477 debug("mrc_input %p\n", pei_data->mrc_input);
480 * Do not pass MRC data in for recovery mode boot,
481 * Always pass it in for S3 resume.
483 if (!recovery_mode_enabled() ||
484 pei_data->boot_mode == PEI_BOOT_RESUME) {
485 ret = prepare_mrc_cache(pei_data);
487 debug("prepare_mrc_cache failed: %d\n", ret);
490 /* If MRC data is not found we cannot continue S3 resume. */
491 if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
492 debug("Giving up in sdram_initialize: No MRC data\n");
496 /* Pass console handler in pei_data */
497 pei_data->tx_byte = sdram_console_tx_byte;
499 /* Wait for ME to be ready */
500 ret = intel_early_me_init(me_dev);
503 ret = intel_early_me_uma_size(me_dev);
507 ret = mrc_common_init(dev, pei_data, false);
511 ret = sdram_find(dev);
514 gd->ram_size = gd->arch.meminfo.total_32bit_memory;
516 debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len,
517 pei_data->mrc_output);
519 post_system_agent_init(dev, me_dev, pei_data);
520 report_memory_config();
522 /* S3 resume: don't save scrambler seed or MRC data */
523 if (pei_data->boot_mode != PEI_BOOT_RESUME) {
525 * This will be copied to SDRAM in reserve_arch(), then written
526 * to SPI flash in mrccache_save()
528 gd->arch.mrc_output = (char *)pei_data->mrc_output;
529 gd->arch.mrc_output_len = pei_data->mrc_output_len;
530 ret = write_seeds_to_cmos(pei_data);
532 debug("Failed to write seeds to CMOS: %d\n", ret);
535 writew(0xCAFE, MCHBAR_REG(SSKPD));