2 * Copyright (C) 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
6 * Based on code from the coreboot file of the same name
14 #include <asm/atomic.h>
16 #include <asm/interrupt.h>
17 #include <asm/lapic.h>
21 #include <asm/processor.h>
23 #include <dm/device-internal.h>
24 #include <dm/uclass-internal.h>
25 #include <linux/linkage.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 /* Total CPUs include BSP */
32 /* This also needs to match the sipi.S assembly code for saved MSR encoding */
40 struct mp_flight_plan {
42 struct mp_flight_record *records;
45 static struct mp_flight_plan mp_info;
53 static inline void barrier_wait(atomic_t *b)
55 while (atomic_read(b) == 0)
60 static inline void release_barrier(atomic_t *b)
66 static inline void stop_this_cpu(void)
68 /* Called by an AP when it is ready to halt and wait for a new task */
73 /* Returns 1 if timeout waiting for APs. 0 if target APs found */
74 static int wait_for_aps(atomic_t *val, int target, int total_delay,
80 while (atomic_read(val) != target) {
82 delayed += delay_step;
83 if (delayed >= total_delay) {
92 static void ap_do_flight_plan(struct udevice *cpu)
96 for (i = 0; i < mp_info.num_records; i++) {
97 struct mp_flight_record *rec = &mp_info.records[i];
99 atomic_inc(&rec->cpus_entered);
100 barrier_wait(&rec->barrier);
102 if (rec->ap_call != NULL)
103 rec->ap_call(cpu, rec->ap_arg);
107 static int find_cpu_by_apid_id(int apic_id, struct udevice **devp)
112 for (uclass_find_first_device(UCLASS_CPU, &dev);
114 uclass_find_next_device(&dev)) {
115 struct cpu_platdata *plat = dev_get_parent_platdata(dev);
117 if (plat->cpu_id == apic_id) {
127 * By the time APs call ap_init() caching has been setup, and microcode has
130 static void ap_init(unsigned int cpu_index)
136 /* Ensure the local apic is enabled */
140 ret = find_cpu_by_apid_id(apic_id, &dev);
142 debug("Unknown CPU apic_id %x\n", apic_id);
146 debug("AP: slot %d apic_id %x, dev %s\n", cpu_index, apic_id,
147 dev ? dev->name : "(apic_id not found)");
149 /* Walk the flight plan */
150 ap_do_flight_plan(dev);
158 static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = {
159 MTRR_FIX_64K_00000_MSR, MTRR_FIX_16K_80000_MSR, MTRR_FIX_16K_A0000_MSR,
160 MTRR_FIX_4K_C0000_MSR, MTRR_FIX_4K_C8000_MSR, MTRR_FIX_4K_D0000_MSR,
161 MTRR_FIX_4K_D8000_MSR, MTRR_FIX_4K_E0000_MSR, MTRR_FIX_4K_E8000_MSR,
162 MTRR_FIX_4K_F0000_MSR, MTRR_FIX_4K_F8000_MSR,
165 static inline struct saved_msr *save_msr(int index, struct saved_msr *entry)
169 msr = msr_read(index);
170 entry->index = index;
174 /* Return the next entry */
179 static int save_bsp_msrs(char *start, int size)
183 struct saved_msr *msr_entry;
187 /* Determine number of MTRRs need to be saved */
188 msr = msr_read(MTRR_CAP_MSR);
189 num_var_mtrrs = msr.lo & 0xff;
191 /* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE */
192 msr_count = 2 * num_var_mtrrs + NUM_FIXED_MTRRS + 1;
194 if ((msr_count * sizeof(struct saved_msr)) > size) {
195 printf("Cannot mirror all %d msrs.\n", msr_count);
199 msr_entry = (void *)start;
200 for (i = 0; i < NUM_FIXED_MTRRS; i++)
201 msr_entry = save_msr(fixed_mtrrs[i], msr_entry);
203 for (i = 0; i < num_var_mtrrs; i++) {
204 msr_entry = save_msr(MTRR_PHYS_BASE_MSR(i), msr_entry);
205 msr_entry = save_msr(MTRR_PHYS_MASK_MSR(i), msr_entry);
208 msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry);
213 static int load_sipi_vector(atomic_t **ap_countp)
215 struct sipi_params_16bit *params16;
216 struct sipi_params *params;
217 static char msr_save[512];
224 /* Copy in the code */
225 code_len = ap_start16_code_end - ap_start16;
226 debug("Copying SIPI code to %x: %d bytes\n", AP_DEFAULT_BASE,
228 memcpy((void *)AP_DEFAULT_BASE, ap_start16, code_len);
230 addr = AP_DEFAULT_BASE + (ulong)sipi_params_16bit - (ulong)ap_start16;
231 params16 = (struct sipi_params_16bit *)addr;
232 params16->ap_start = (uint32_t)ap_start;
233 params16->gdt = (uint32_t)gd->arch.gdt;
234 params16->gdt_limit = X86_GDT_SIZE - 1;
235 debug("gdt = %x, gdt_limit = %x\n", params16->gdt, params16->gdt_limit);
237 params = (struct sipi_params *)sipi_params;
238 debug("SIPI 32-bit params at %p\n", params);
239 params->idt_ptr = (uint32_t)x86_get_idt();
241 params->stack_size = CONFIG_AP_STACK_SIZE;
242 size = params->stack_size * CONFIG_MAX_CPUS;
243 stack = memalign(size, 4096);
246 params->stack_top = (u32)(stack + size);
248 params->microcode_ptr = 0;
249 params->msr_table_ptr = (u32)msr_save;
250 ret = save_bsp_msrs(msr_save, sizeof(msr_save));
253 params->msr_count = ret;
255 params->c_handler = (uint32_t)&ap_init;
257 *ap_countp = ¶ms->ap_count;
258 atomic_set(*ap_countp, 0);
259 debug("SIPI vector is ready\n");
264 static int check_cpu_devices(int expected_cpus)
268 for (i = 0; i < expected_cpus; i++) {
272 ret = uclass_find_device(UCLASS_CPU, i, &dev);
274 debug("Cannot find CPU %d in device tree\n", i);
282 /* Returns 1 for timeout. 0 on success */
283 static int apic_wait_timeout(int total_delay, int delay_step)
288 while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY) {
291 if (total >= total_delay) {
300 static int start_aps(int ap_count, atomic_t *num_aps)
303 /* Max location is 4KiB below 1MiB */
304 const int max_vector_loc = ((1 << 20) - (1 << 12)) >> 12;
309 /* The vector is sent as a 4k aligned address in one byte */
310 sipi_vector = AP_DEFAULT_BASE >> 12;
312 if (sipi_vector > max_vector_loc) {
313 printf("SIPI vector too large! 0x%08x\n",
318 debug("Attempting to start %d APs\n", ap_count);
320 if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
321 debug("Waiting for ICR not to be busy...");
322 if (apic_wait_timeout(1000, 50)) {
323 debug("timed out. Aborting.\n");
330 /* Send INIT IPI to all but self */
331 lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
332 lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
334 debug("Waiting for 10ms after sending INIT.\n");
338 if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
339 debug("Waiting for ICR not to be busy...");
340 if (apic_wait_timeout(1000, 50)) {
341 debug("timed out. Aborting.\n");
348 lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
349 lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
350 LAPIC_DM_STARTUP | sipi_vector);
351 debug("Waiting for 1st SIPI to complete...");
352 if (apic_wait_timeout(10000, 50)) {
353 debug("timed out.\n");
359 /* Wait for CPUs to check in up to 200 us */
360 wait_for_aps(num_aps, ap_count, 200, 15);
363 if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
364 debug("Waiting for ICR not to be busy...");
365 if (apic_wait_timeout(1000, 50)) {
366 debug("timed out. Aborting.\n");
373 lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
374 lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
375 LAPIC_DM_STARTUP | sipi_vector);
376 debug("Waiting for 2nd SIPI to complete...");
377 if (apic_wait_timeout(10000, 50)) {
378 debug("timed out.\n");
384 /* Wait for CPUs to check in */
385 if (wait_for_aps(num_aps, ap_count, 10000, 50)) {
386 debug("Not all APs checked in: %d/%d.\n",
387 atomic_read(num_aps), ap_count);
394 static int bsp_do_flight_plan(struct udevice *cpu, struct mp_params *mp_params)
398 const int timeout_us = 100000;
399 const int step_us = 100;
400 int num_aps = num_cpus - 1;
402 for (i = 0; i < mp_params->num_records; i++) {
403 struct mp_flight_record *rec = &mp_params->flight_plan[i];
405 /* Wait for APs if the record is not released */
406 if (atomic_read(&rec->barrier) == 0) {
407 /* Wait for the APs to check in */
408 if (wait_for_aps(&rec->cpus_entered, num_aps,
409 timeout_us, step_us)) {
410 debug("MP record %d timeout.\n", i);
415 if (rec->bsp_call != NULL)
416 rec->bsp_call(cpu, rec->bsp_arg);
418 release_barrier(&rec->barrier);
423 static int init_bsp(struct udevice **devp)
425 char processor_name[CPU_MAX_NAME_LEN];
429 cpu_get_name(processor_name);
430 debug("CPU: %s.\n", processor_name);
435 ret = find_cpu_by_apid_id(apic_id, devp);
437 printf("Cannot find boot CPU, APIC ID %d\n", apic_id);
444 int mp_init(struct mp_params *p)
451 /* This will cause the CPUs devices to be bound */
453 ret = uclass_get(UCLASS_CPU, &uc);
457 ret = init_bsp(&cpu);
459 debug("Cannot init boot CPU: err=%d\n", ret);
463 if (p == NULL || p->flight_plan == NULL || p->num_records < 1) {
464 printf("Invalid MP parameters\n");
468 num_cpus = cpu_get_count(cpu);
470 debug("Cannot get number of CPUs: err=%d\n", num_cpus);
475 debug("Warning: Only 1 CPU is detected\n");
477 ret = check_cpu_devices(num_cpus);
479 debug("Warning: Device tree does not describe all CPUs. Extra ones will not be started correctly\n");
481 /* Copy needed parameters so that APs have a reference to the plan */
482 mp_info.num_records = p->num_records;
483 mp_info.records = p->flight_plan;
485 /* Load the SIPI vector */
486 ret = load_sipi_vector(&ap_count);
487 if (ap_count == NULL)
491 * Make sure SIPI data hits RAM so the APs that come up will see
492 * the startup code even if the caches are disabled
496 /* Start the APs providing number of APs and the cpus_entered field */
497 num_aps = num_cpus - 1;
498 ret = start_aps(num_aps, ap_count);
501 debug("%d/%d eventually checked in?\n", atomic_read(ap_count),
506 /* Walk the flight plan for the BSP */
507 ret = bsp_do_flight_plan(cpu, p);
509 debug("CPU init failed: err=%d\n", ret);
516 int mp_init_cpu(struct udevice *cpu, void *unused)
519 * Multiple APs are brought up simultaneously and they may get the same
520 * seq num in the uclass_resolve_seq() during device_probe(). To avoid
521 * this, set req_seq to the reg number in the device tree in advance.
523 cpu->req_seq = fdtdec_get_int(gd->fdt_blob, cpu->of_offset, "reg", -1);
525 return device_probe(cpu);