2 * Copyright (C) 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
6 * Based on code from the coreboot file of the same name
14 #include <asm/atomic.h>
16 #include <asm/interrupt.h>
17 #include <asm/lapic.h>
21 #include <asm/processor.h>
23 #include <dm/device-internal.h>
24 #include <dm/uclass-internal.h>
25 #include <linux/linkage.h>
27 /* Total CPUs include BSP */
30 /* This also needs to match the sipi.S assembly code for saved MSR encoding */
38 struct mp_flight_plan {
40 struct mp_flight_record *records;
43 static struct mp_flight_plan mp_info;
51 static inline void barrier_wait(atomic_t *b)
53 while (atomic_read(b) == 0)
58 static inline void release_barrier(atomic_t *b)
64 static inline void stop_this_cpu(void)
66 /* Called by an AP when it is ready to halt and wait for a new task */
71 /* Returns 1 if timeout waiting for APs. 0 if target APs found */
72 static int wait_for_aps(atomic_t *val, int target, int total_delay,
78 while (atomic_read(val) != target) {
80 delayed += delay_step;
81 if (delayed >= total_delay) {
90 static void ap_do_flight_plan(struct udevice *cpu)
94 for (i = 0; i < mp_info.num_records; i++) {
95 struct mp_flight_record *rec = &mp_info.records[i];
97 atomic_inc(&rec->cpus_entered);
98 barrier_wait(&rec->barrier);
100 if (rec->ap_call != NULL)
101 rec->ap_call(cpu, rec->ap_arg);
105 static int find_cpu_by_apid_id(int apic_id, struct udevice **devp)
110 for (uclass_find_first_device(UCLASS_CPU, &dev);
112 uclass_find_next_device(&dev)) {
113 struct cpu_platdata *plat = dev_get_parent_platdata(dev);
115 if (plat->cpu_id == apic_id) {
125 * By the time APs call ap_init() caching has been setup, and microcode has
128 static void ap_init(unsigned int cpu_index)
134 /* Ensure the local apic is enabled */
138 ret = find_cpu_by_apid_id(apic_id, &dev);
140 debug("Unknown CPU apic_id %x\n", apic_id);
144 debug("AP: slot %d apic_id %x, dev %s\n", cpu_index, apic_id,
145 dev ? dev->name : "(apic_id not found)");
147 /* Walk the flight plan */
148 ap_do_flight_plan(dev);
156 static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = {
157 MTRR_FIX_64K_00000_MSR, MTRR_FIX_16K_80000_MSR, MTRR_FIX_16K_A0000_MSR,
158 MTRR_FIX_4K_C0000_MSR, MTRR_FIX_4K_C8000_MSR, MTRR_FIX_4K_D0000_MSR,
159 MTRR_FIX_4K_D8000_MSR, MTRR_FIX_4K_E0000_MSR, MTRR_FIX_4K_E8000_MSR,
160 MTRR_FIX_4K_F0000_MSR, MTRR_FIX_4K_F8000_MSR,
163 static inline struct saved_msr *save_msr(int index, struct saved_msr *entry)
167 msr = msr_read(index);
168 entry->index = index;
172 /* Return the next entry */
177 static int save_bsp_msrs(char *start, int size)
181 struct saved_msr *msr_entry;
185 /* Determine number of MTRRs need to be saved */
186 msr = msr_read(MTRR_CAP_MSR);
187 num_var_mtrrs = msr.lo & 0xff;
189 /* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE */
190 msr_count = 2 * num_var_mtrrs + NUM_FIXED_MTRRS + 1;
192 if ((msr_count * sizeof(struct saved_msr)) > size) {
193 printf("Cannot mirror all %d msrs.\n", msr_count);
197 msr_entry = (void *)start;
198 for (i = 0; i < NUM_FIXED_MTRRS; i++)
199 msr_entry = save_msr(fixed_mtrrs[i], msr_entry);
201 for (i = 0; i < num_var_mtrrs; i++) {
202 msr_entry = save_msr(MTRR_PHYS_BASE_MSR(i), msr_entry);
203 msr_entry = save_msr(MTRR_PHYS_MASK_MSR(i), msr_entry);
206 msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry);
211 static int load_sipi_vector(atomic_t **ap_countp)
213 struct sipi_params_16bit *params16;
214 struct sipi_params *params;
215 static char msr_save[512];
222 /* Copy in the code */
223 code_len = ap_start16_code_end - ap_start16;
224 debug("Copying SIPI code to %x: %d bytes\n", AP_DEFAULT_BASE,
226 memcpy((void *)AP_DEFAULT_BASE, ap_start16, code_len);
228 addr = AP_DEFAULT_BASE + (ulong)sipi_params_16bit - (ulong)ap_start16;
229 params16 = (struct sipi_params_16bit *)addr;
230 params16->ap_start = (uint32_t)ap_start;
231 params16->gdt = (uint32_t)gd->arch.gdt;
232 params16->gdt_limit = X86_GDT_SIZE - 1;
233 debug("gdt = %x, gdt_limit = %x\n", params16->gdt, params16->gdt_limit);
235 params = (struct sipi_params *)sipi_params;
236 debug("SIPI 32-bit params at %p\n", params);
237 params->idt_ptr = (uint32_t)x86_get_idt();
239 params->stack_size = CONFIG_AP_STACK_SIZE;
240 size = params->stack_size * CONFIG_MAX_CPUS;
241 stack = memalign(size, 4096);
244 params->stack_top = (u32)(stack + size);
246 params->microcode_ptr = 0;
247 params->msr_table_ptr = (u32)msr_save;
248 ret = save_bsp_msrs(msr_save, sizeof(msr_save));
251 params->msr_count = ret;
253 params->c_handler = (uint32_t)&ap_init;
255 *ap_countp = ¶ms->ap_count;
256 atomic_set(*ap_countp, 0);
257 debug("SIPI vector is ready\n");
262 static int check_cpu_devices(int expected_cpus)
266 for (i = 0; i < expected_cpus; i++) {
270 ret = uclass_find_device(UCLASS_CPU, i, &dev);
272 debug("Cannot find CPU %d in device tree\n", i);
280 /* Returns 1 for timeout. 0 on success */
281 static int apic_wait_timeout(int total_delay, int delay_step)
286 while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY) {
289 if (total >= total_delay) {
298 static int start_aps(int ap_count, atomic_t *num_aps)
301 /* Max location is 4KiB below 1MiB */
302 const int max_vector_loc = ((1 << 20) - (1 << 12)) >> 12;
307 /* The vector is sent as a 4k aligned address in one byte */
308 sipi_vector = AP_DEFAULT_BASE >> 12;
310 if (sipi_vector > max_vector_loc) {
311 printf("SIPI vector too large! 0x%08x\n",
316 debug("Attempting to start %d APs\n", ap_count);
318 if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
319 debug("Waiting for ICR not to be busy...");
320 if (apic_wait_timeout(1000, 50)) {
321 debug("timed out. Aborting.\n");
328 /* Send INIT IPI to all but self */
329 lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
330 lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
332 debug("Waiting for 10ms after sending INIT.\n");
336 if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
337 debug("Waiting for ICR not to be busy...");
338 if (apic_wait_timeout(1000, 50)) {
339 debug("timed out. Aborting.\n");
346 lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
347 lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
348 LAPIC_DM_STARTUP | sipi_vector);
349 debug("Waiting for 1st SIPI to complete...");
350 if (apic_wait_timeout(10000, 50)) {
351 debug("timed out.\n");
357 /* Wait for CPUs to check in up to 200 us */
358 wait_for_aps(num_aps, ap_count, 200, 15);
361 if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
362 debug("Waiting for ICR not to be busy...");
363 if (apic_wait_timeout(1000, 50)) {
364 debug("timed out. Aborting.\n");
371 lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
372 lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
373 LAPIC_DM_STARTUP | sipi_vector);
374 debug("Waiting for 2nd SIPI to complete...");
375 if (apic_wait_timeout(10000, 50)) {
376 debug("timed out.\n");
382 /* Wait for CPUs to check in */
383 if (wait_for_aps(num_aps, ap_count, 10000, 50)) {
384 debug("Not all APs checked in: %d/%d.\n",
385 atomic_read(num_aps), ap_count);
392 static int bsp_do_flight_plan(struct udevice *cpu, struct mp_params *mp_params)
396 const int timeout_us = 100000;
397 const int step_us = 100;
398 int num_aps = num_cpus - 1;
400 for (i = 0; i < mp_params->num_records; i++) {
401 struct mp_flight_record *rec = &mp_params->flight_plan[i];
403 /* Wait for APs if the record is not released */
404 if (atomic_read(&rec->barrier) == 0) {
405 /* Wait for the APs to check in */
406 if (wait_for_aps(&rec->cpus_entered, num_aps,
407 timeout_us, step_us)) {
408 debug("MP record %d timeout.\n", i);
413 if (rec->bsp_call != NULL)
414 rec->bsp_call(cpu, rec->bsp_arg);
416 release_barrier(&rec->barrier);
421 static int init_bsp(struct udevice **devp)
423 char processor_name[CPU_MAX_NAME_LEN];
427 cpu_get_name(processor_name);
428 debug("CPU: %s.\n", processor_name);
433 ret = find_cpu_by_apid_id(apic_id, devp);
435 printf("Cannot find boot CPU, APIC ID %d\n", apic_id);
442 int mp_init(struct mp_params *p)
449 /* This will cause the CPUs devices to be bound */
451 ret = uclass_get(UCLASS_CPU, &uc);
455 ret = init_bsp(&cpu);
457 debug("Cannot init boot CPU: err=%d\n", ret);
461 if (p == NULL || p->flight_plan == NULL || p->num_records < 1) {
462 printf("Invalid MP parameters\n");
466 num_cpus = cpu_get_count(cpu);
468 debug("Cannot get number of CPUs: err=%d\n", num_cpus);
473 debug("Warning: Only 1 CPU is detected\n");
475 ret = check_cpu_devices(num_cpus);
477 debug("Warning: Device tree does not describe all CPUs. Extra ones will not be started correctly\n");
479 /* Copy needed parameters so that APs have a reference to the plan */
480 mp_info.num_records = p->num_records;
481 mp_info.records = p->flight_plan;
483 /* Load the SIPI vector */
484 ret = load_sipi_vector(&ap_count);
485 if (ap_count == NULL)
489 * Make sure SIPI data hits RAM so the APs that come up will see
490 * the startup code even if the caches are disabled
494 /* Start the APs providing number of APs and the cpus_entered field */
495 num_aps = num_cpus - 1;
496 ret = start_aps(num_aps, ap_count);
499 debug("%d/%d eventually checked in?\n", atomic_read(ap_count),
504 /* Walk the flight plan for the BSP */
505 ret = bsp_do_flight_plan(cpu, p);
507 debug("CPU init failed: err=%d\n", ret);
514 int mp_init_cpu(struct udevice *cpu, void *unused)
516 return device_probe(cpu);