2 * Copyright (C) 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
6 * Based on code from the coreboot file of the same name
14 #include <asm/atomic.h>
16 #include <asm/interrupt.h>
17 #include <asm/lapic.h>
21 #include <dm/device-internal.h>
22 #include <dm/uclass-internal.h>
23 #include <linux/linkage.h>
25 /* This also needs to match the sipi.S assembly code for saved MSR encoding */
33 struct mp_flight_plan {
35 struct mp_flight_record *records;
38 static struct mp_flight_plan mp_info;
46 static inline void barrier_wait(atomic_t *b)
48 while (atomic_read(b) == 0)
53 static inline void release_barrier(atomic_t *b)
59 /* Returns 1 if timeout waiting for APs. 0 if target APs found */
60 static int wait_for_aps(atomic_t *val, int target, int total_delay,
66 while (atomic_read(val) != target) {
68 delayed += delay_step;
69 if (delayed >= total_delay) {
78 static void ap_do_flight_plan(struct udevice *cpu)
82 for (i = 0; i < mp_info.num_records; i++) {
83 struct mp_flight_record *rec = &mp_info.records[i];
85 atomic_inc(&rec->cpus_entered);
86 barrier_wait(&rec->barrier);
88 if (rec->ap_call != NULL)
89 rec->ap_call(cpu, rec->ap_arg);
93 static int find_cpu_by_apid_id(int apic_id, struct udevice **devp)
98 for (uclass_find_first_device(UCLASS_CPU, &dev);
100 uclass_find_next_device(&dev)) {
101 struct cpu_platdata *plat = dev_get_parent_platdata(dev);
103 if (plat->cpu_id == apic_id) {
113 * By the time APs call ap_init() caching has been setup, and microcode has
116 static void ap_init(unsigned int cpu_index)
122 /* Ensure the local apic is enabled */
126 ret = find_cpu_by_apid_id(apic_id, &dev);
128 debug("Unknown CPU apic_id %x\n", apic_id);
132 debug("AP: slot %d apic_id %x, dev %s\n", cpu_index, apic_id,
133 dev ? dev->name : "(apic_id not found)");
135 /* Walk the flight plan */
136 ap_do_flight_plan(dev);
144 static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = {
145 MTRR_FIX_64K_00000_MSR, MTRR_FIX_16K_80000_MSR, MTRR_FIX_16K_A0000_MSR,
146 MTRR_FIX_4K_C0000_MSR, MTRR_FIX_4K_C8000_MSR, MTRR_FIX_4K_D0000_MSR,
147 MTRR_FIX_4K_D8000_MSR, MTRR_FIX_4K_E0000_MSR, MTRR_FIX_4K_E8000_MSR,
148 MTRR_FIX_4K_F0000_MSR, MTRR_FIX_4K_F8000_MSR,
151 static inline struct saved_msr *save_msr(int index, struct saved_msr *entry)
155 msr = msr_read(index);
156 entry->index = index;
160 /* Return the next entry */
165 static int save_bsp_msrs(char *start, int size)
169 struct saved_msr *msr_entry;
173 /* Determine number of MTRRs need to be saved */
174 msr = msr_read(MTRR_CAP_MSR);
175 num_var_mtrrs = msr.lo & 0xff;
177 /* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE */
178 msr_count = 2 * num_var_mtrrs + NUM_FIXED_MTRRS + 1;
180 if ((msr_count * sizeof(struct saved_msr)) > size) {
181 printf("Cannot mirror all %d msrs.\n", msr_count);
185 msr_entry = (void *)start;
186 for (i = 0; i < NUM_FIXED_MTRRS; i++)
187 msr_entry = save_msr(fixed_mtrrs[i], msr_entry);
189 for (i = 0; i < num_var_mtrrs; i++) {
190 msr_entry = save_msr(MTRR_PHYS_BASE_MSR(i), msr_entry);
191 msr_entry = save_msr(MTRR_PHYS_MASK_MSR(i), msr_entry);
194 msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry);
199 static int load_sipi_vector(atomic_t **ap_countp)
201 struct sipi_params_16bit *params16;
202 struct sipi_params *params;
203 static char msr_save[512];
210 /* Copy in the code */
211 code_len = ap_start16_code_end - ap_start16;
212 debug("Copying SIPI code to %x: %d bytes\n", AP_DEFAULT_BASE,
214 memcpy((void *)AP_DEFAULT_BASE, ap_start16, code_len);
216 addr = AP_DEFAULT_BASE + (ulong)sipi_params_16bit - (ulong)ap_start16;
217 params16 = (struct sipi_params_16bit *)addr;
218 params16->ap_start = (uint32_t)ap_start;
219 params16->gdt = (uint32_t)gd->arch.gdt;
220 params16->gdt_limit = X86_GDT_SIZE - 1;
221 debug("gdt = %x, gdt_limit = %x\n", params16->gdt, params16->gdt_limit);
223 params = (struct sipi_params *)sipi_params;
224 debug("SIPI 32-bit params at %p\n", params);
225 params->idt_ptr = (uint32_t)x86_get_idt();
227 params->stack_size = CONFIG_AP_STACK_SIZE;
228 size = params->stack_size * CONFIG_MAX_CPUS;
229 stack = memalign(size, 4096);
232 params->stack_top = (u32)(stack + size);
234 params->microcode_ptr = 0;
235 params->msr_table_ptr = (u32)msr_save;
236 ret = save_bsp_msrs(msr_save, sizeof(msr_save));
239 params->msr_count = ret;
241 params->c_handler = (uint32_t)&ap_init;
243 *ap_countp = ¶ms->ap_count;
244 atomic_set(*ap_countp, 0);
245 debug("SIPI vector is ready\n");
250 static int check_cpu_devices(int expected_cpus)
254 for (i = 0; i < expected_cpus; i++) {
258 ret = uclass_find_device(UCLASS_CPU, i, &dev);
260 debug("Cannot find CPU %d in device tree\n", i);
268 /* Returns 1 for timeout. 0 on success */
269 static int apic_wait_timeout(int total_delay, int delay_step)
274 while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY) {
277 if (total >= total_delay) {
286 static int start_aps(int ap_count, atomic_t *num_aps)
289 /* Max location is 4KiB below 1MiB */
290 const int max_vector_loc = ((1 << 20) - (1 << 12)) >> 12;
295 /* The vector is sent as a 4k aligned address in one byte */
296 sipi_vector = AP_DEFAULT_BASE >> 12;
298 if (sipi_vector > max_vector_loc) {
299 printf("SIPI vector too large! 0x%08x\n",
304 debug("Attempting to start %d APs\n", ap_count);
306 if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
307 debug("Waiting for ICR not to be busy...");
308 if (apic_wait_timeout(1000, 50)) {
309 debug("timed out. Aborting.\n");
316 /* Send INIT IPI to all but self */
317 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
318 lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
320 debug("Waiting for 10ms after sending INIT.\n");
324 if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
325 debug("Waiting for ICR not to be busy...");
326 if (apic_wait_timeout(1000, 50)) {
327 debug("timed out. Aborting.\n");
334 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
335 lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
336 LAPIC_DM_STARTUP | sipi_vector);
337 debug("Waiting for 1st SIPI to complete...");
338 if (apic_wait_timeout(10000, 50)) {
339 debug("timed out.\n");
345 /* Wait for CPUs to check in up to 200 us */
346 wait_for_aps(num_aps, ap_count, 200, 15);
349 if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
350 debug("Waiting for ICR not to be busy...");
351 if (apic_wait_timeout(1000, 50)) {
352 debug("timed out. Aborting.\n");
359 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
360 lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
361 LAPIC_DM_STARTUP | sipi_vector);
362 debug("Waiting for 2nd SIPI to complete...");
363 if (apic_wait_timeout(10000, 50)) {
364 debug("timed out.\n");
370 /* Wait for CPUs to check in */
371 if (wait_for_aps(num_aps, ap_count, 10000, 50)) {
372 debug("Not all APs checked in: %d/%d.\n",
373 atomic_read(num_aps), ap_count);
380 static int bsp_do_flight_plan(struct udevice *cpu, struct mp_params *mp_params)
384 const int timeout_us = 100000;
385 const int step_us = 100;
386 int num_aps = mp_params->num_cpus - 1;
388 for (i = 0; i < mp_params->num_records; i++) {
389 struct mp_flight_record *rec = &mp_params->flight_plan[i];
391 /* Wait for APs if the record is not released */
392 if (atomic_read(&rec->barrier) == 0) {
393 /* Wait for the APs to check in */
394 if (wait_for_aps(&rec->cpus_entered, num_aps,
395 timeout_us, step_us)) {
396 debug("MP record %d timeout.\n", i);
401 if (rec->bsp_call != NULL)
402 rec->bsp_call(cpu, rec->bsp_arg);
404 release_barrier(&rec->barrier);
409 static int init_bsp(struct udevice **devp)
411 char processor_name[CPU_MAX_NAME_LEN];
415 cpu_get_name(processor_name);
416 debug("CPU: %s.\n", processor_name);
421 ret = find_cpu_by_apid_id(apic_id, devp);
423 printf("Cannot find boot CPU, APIC ID %d\n", apic_id);
430 int mp_init(struct mp_params *p)
437 /* This will cause the CPUs devices to be bound */
439 ret = uclass_get(UCLASS_CPU, &uc);
443 ret = init_bsp(&cpu);
445 debug("Cannot init boot CPU: err=%d\n", ret);
449 if (p == NULL || p->flight_plan == NULL || p->num_records < 1) {
450 printf("Invalid MP parameters\n");
454 ret = check_cpu_devices(p->num_cpus);
456 debug("Warning: Device tree does not describe all CPUs. Extra ones will not be started correctly\n");
458 /* Copy needed parameters so that APs have a reference to the plan */
459 mp_info.num_records = p->num_records;
460 mp_info.records = p->flight_plan;
462 /* Load the SIPI vector */
463 ret = load_sipi_vector(&ap_count);
464 if (ap_count == NULL)
468 * Make sure SIPI data hits RAM so the APs that come up will see
469 * the startup code even if the caches are disabled
473 /* Start the APs providing number of APs and the cpus_entered field */
474 num_aps = p->num_cpus - 1;
475 ret = start_aps(num_aps, ap_count);
478 debug("%d/%d eventually checked in?\n", atomic_read(ap_count),
483 /* Walk the flight plan for the BSP */
484 ret = bsp_do_flight_plan(cpu, p);
486 debug("CPU init failed: err=%d\n", ret);
493 int mp_init_cpu(struct udevice *cpu, void *unused)
495 return device_probe(cpu);