2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2008,2009
4 * Graeme Russ, <graeme.russ@gmail.com>
7 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
9 * SPDX-License-Identifier: GPL-2.0+
20 DECLARE_GLOBAL_DATA_PTR;
22 static struct pci_controller x86_hose;
24 int pci_early_init_hose(struct pci_controller **hosep)
26 struct pci_controller *hose;
28 hose = calloc(1, sizeof(struct pci_controller));
32 board_pci_setup_hose(hose);
33 pci_setup_type1(hose);
34 hose->last_busno = pci_hose_scan(hose);
41 __weak int board_pci_pre_scan(struct pci_controller *hose)
46 __weak int board_pci_post_scan(struct pci_controller *hose)
51 void pci_init_board(void)
53 struct pci_controller *hose = &x86_hose;
55 /* Stop using the early hose */
58 board_pci_setup_hose(hose);
59 pci_setup_type1(hose);
60 pci_register_hose(hose);
62 board_pci_pre_scan(hose);
63 hose->last_busno = pci_hose_scan(hose);
64 board_pci_post_scan(hose);
67 static struct pci_controller *get_hose(void)
72 return pci_bus_to_hose(0);
75 unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where)
79 if (pci_hose_read_config_byte(get_hose(), dev, where, &value))
85 unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where)
89 if (pci_hose_read_config_word(get_hose(), dev, where, &value))
95 unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where)
99 if (pci_hose_read_config_dword(get_hose(), dev, where, &value))
105 void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
107 pci_hose_write_config_byte(get_hose(), dev, where, value);
110 void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
112 pci_hose_write_config_word(get_hose(), dev, where, value);
115 void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
117 pci_hose_write_config_dword(get_hose(), dev, where, value);
120 int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
121 ulong *valuep, enum pci_size_t size)
123 outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
126 *valuep = inb(PCI_REG_DATA + (offset & 3));
129 *valuep = inw(PCI_REG_DATA + (offset & 2));
132 *valuep = inl(PCI_REG_DATA);
139 int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
140 ulong value, enum pci_size_t size)
142 outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
145 outb(value, PCI_REG_DATA + (offset & 3));
148 outw(value, PCI_REG_DATA + (offset & 2));
151 outl(value, PCI_REG_DATA);
158 void pci_assign_irqs(int bus, int device, u8 irq[4])
165 for (func = 0; func < 8; func++) {
166 bdf = PCI_BDF(bus, device, func);
167 vendor = x86_pci_read_config16(bdf, PCI_VENDOR_ID);
168 if (vendor == 0xffff || vendor == 0x0000)
171 pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN);
173 /* PCI spec says all values except 1..4 are reserved */
174 if ((pin < 1) || (pin > 4))
181 debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n",
182 line, bus, device, func, 'A' + pin - 1);
184 x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line);