2 * Copyright (C) 2013, Intel Corporation
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
5 * Ported from Intel released Quark UEFI BIOS
6 * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
8 * SPDX-License-Identifier: Intel
12 #include <asm/arch/mrc.h>
13 #include <asm/arch/msg_port.h>
18 * Enable HTE to detect all possible errors for the given training parameters
19 * (per-bit or full byte lane).
21 static void hte_enable_all_errors(void)
23 msg_port_write(HTE, 0x000200a2, 0xffffffff);
24 msg_port_write(HTE, 0x000200a3, 0x000000ff);
25 msg_port_write(HTE, 0x000200a4, 0x00000000);
29 * Go and read the HTE register in order to find any error
31 * @return: The errors detected in the HTE status register
33 static u32 hte_check_errors(void)
35 return msg_port_read(HTE, 0x000200a7);
39 * Wait until HTE finishes
41 static void hte_wait_for_complete(void)
47 do {} while ((msg_port_read(HTE, 0x00020012) & (1 << 30)) != 0);
49 tmp = msg_port_read(HTE, 0x00020011);
51 tmp &= ~((1 << 12) | (1 << 13));
52 msg_port_write(HTE, 0x00020011, tmp);
58 * Clear registers related with errors in the HTE
60 static void hte_clear_error_regs(void)
65 * Clear all HTE errors and enable error checking
66 * for burst and chunk.
68 tmp = msg_port_read(HTE, 0x000200a1);
70 msg_port_write(HTE, 0x000200a1, tmp);
74 * Execute a basic single-cache-line memory write/read/verify test using simple
75 * constant pattern, different for READ_TRAIN and WRITE_TRAIN modes.
77 * See hte_basic_write_read() which is the external visible wrapper.
79 * @mrc_params: host structure for all MRC global data
80 * @addr: memory adress being tested (must hit specific channel/rank)
81 * @first_run: if set then the HTE registers are configured, otherwise it is
82 * assumed configuration is done and we just re-run the test
83 * @mode: READ_TRAIN or WRITE_TRAIN (the difference is in the pattern)
85 * @return: byte lane failure on each bit (for Quark only bit0 and bit1)
87 static u16 hte_basic_data_cmp(struct mrc_params *mrc_params, u32 addr,
88 u8 first_run, u8 mode)
94 msg_port_write(HTE, 0x00020020, 0x01b10021);
95 msg_port_write(HTE, 0x00020021, 0x06000000);
96 msg_port_write(HTE, 0x00020022, addr >> 6);
97 msg_port_write(HTE, 0x00020062, 0x00800015);
98 msg_port_write(HTE, 0x00020063, 0xaaaaaaaa);
99 msg_port_write(HTE, 0x00020064, 0xcccccccc);
100 msg_port_write(HTE, 0x00020065, 0xf0f0f0f0);
101 msg_port_write(HTE, 0x00020061, 0x00030008);
103 if (mode == WRITE_TRAIN)
104 pattern = 0xc33c0000;
105 else /* READ_TRAIN */
106 pattern = 0xaa5555aa;
108 for (offset = 0x80; offset <= 0x8f; offset++)
109 msg_port_write(HTE, offset, pattern);
112 msg_port_write(HTE, 0x000200a1, 0xffff1000);
113 msg_port_write(HTE, 0x00020011, 0x00011000);
114 msg_port_write(HTE, 0x00020011, 0x00011100);
116 hte_wait_for_complete();
119 * Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for
120 * any bytelane errors.
122 return (hte_check_errors() >> 8) & 0xff;
126 * Examine a single-cache-line memory with write/read/verify test using multiple
127 * data patterns (victim-aggressor algorithm).
129 * See hte_write_stress_bit_lanes() which is the external visible wrapper.
131 * @mrc_params: host structure for all MRC global data
132 * @addr: memory adress being tested (must hit specific channel/rank)
133 * @loop_cnt: number of test iterations
134 * @seed_victim: victim data pattern seed
135 * @seed_aggressor: aggressor data pattern seed
136 * @victim_bit: should be 0 as auto-rotate feature is in use
137 * @first_run: if set then the HTE registers are configured, otherwise it is
138 * assumed configuration is done and we just re-run the test
140 * @return: byte lane failure on each bit (for Quark only bit0 and bit1)
142 static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr,
143 u8 loop_cnt, u32 seed_victim, u32 seed_aggressor,
144 u8 victim_bit, u8 first_run)
150 msg_port_write(HTE, 0x00020020, 0x00910024);
151 msg_port_write(HTE, 0x00020023, 0x00810024);
152 msg_port_write(HTE, 0x00020021, 0x06070000);
153 msg_port_write(HTE, 0x00020024, 0x06070000);
154 msg_port_write(HTE, 0x00020022, addr >> 6);
155 msg_port_write(HTE, 0x00020025, addr >> 6);
156 msg_port_write(HTE, 0x00020062, 0x0000002a);
157 msg_port_write(HTE, 0x00020063, seed_victim);
158 msg_port_write(HTE, 0x00020064, seed_aggressor);
159 msg_port_write(HTE, 0x00020065, seed_victim);
162 * Write the pattern buffers to select the victim bit
166 for (offset = 0x80; offset <= 0x8f; offset++) {
167 if ((offset % 8) == victim_bit)
168 msg_port_write(HTE, offset, 0x55555555);
170 msg_port_write(HTE, offset, 0xcccccccc);
173 msg_port_write(HTE, 0x00020061, 0x00000000);
174 msg_port_write(HTE, 0x00020066, 0x03440000);
175 msg_port_write(HTE, 0x000200a1, 0xffff1000);
178 tmp = 0x10001000 | (loop_cnt << 16);
179 msg_port_write(HTE, 0x00020011, tmp);
180 msg_port_write(HTE, 0x00020011, tmp | (1 << 8));
182 hte_wait_for_complete();
185 * Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for
186 * any bytelane errors.
188 return (hte_check_errors() >> 8) & 0xff;
192 * Use HW HTE engine to initialize or test all memory attached to a given DUNIT.
193 * If flag is MRC_MEM_INIT, this routine writes 0s to all memory locations to
194 * initialize ECC. If flag is MRC_MEM_TEST, this routine will send an 5AA55AA5
195 * pattern to all memory locations on the RankMask and then read it back.
196 * Then it sends an A55AA55A pattern to all memory locations on the RankMask
199 * @mrc_params: host structure for all MRC global data
200 * @flag: MRC_MEM_INIT or MRC_MEM_TEST
202 * @return: errors register showing HTE failures. Also prints out which rank
203 * failed the HTE test if failure occurs. For rank detection to work,
204 * the address map must be left in its default state. If MRC changes
205 * the address map, this function must be modified to change it back
206 * to default at the beginning, then restore it at the end.
208 u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag)
215 * Clear out the error registers at the start of each memory
216 * init or memory test run.
218 hte_clear_error_regs();
220 msg_port_write(HTE, 0x00020062, 0x00000015);
222 for (offset = 0x80; offset <= 0x8f; offset++)
223 msg_port_write(HTE, offset, ((offset & 1) ? 0xa55a : 0x5aa5));
225 msg_port_write(HTE, 0x00020021, 0x00000000);
226 msg_port_write(HTE, 0x00020022, (mrc_params->mem_size >> 6) - 1);
227 msg_port_write(HTE, 0x00020063, 0xaaaaaaaa);
228 msg_port_write(HTE, 0x00020064, 0xcccccccc);
229 msg_port_write(HTE, 0x00020065, 0xf0f0f0f0);
230 msg_port_write(HTE, 0x00020066, 0x03000000);
235 * Only 1 write pass through memory is needed
241 /* Write/read then write/read with inverted pattern */
245 DPF(D_INFO, "Unknown parameter for flag: %d\n", flag);
249 DPF(D_INFO, "hte_mem_init");
251 for (i = 0; i < test_num; i++) {
255 msg_port_write(HTE, 0x00020061, 0x00000000);
256 msg_port_write(HTE, 0x00020020, 0x00110010);
258 msg_port_write(HTE, 0x00020061, 0x00000000);
259 msg_port_write(HTE, 0x00020020, 0x00010010);
261 msg_port_write(HTE, 0x00020061, 0x00010100);
262 msg_port_write(HTE, 0x00020020, 0x00110010);
264 msg_port_write(HTE, 0x00020061, 0x00010100);
265 msg_port_write(HTE, 0x00020020, 0x00010010);
268 msg_port_write(HTE, 0x00020011, 0x00111000);
269 msg_port_write(HTE, 0x00020011, 0x00111100);
271 hte_wait_for_complete();
273 /* If this is a READ pass, check for errors at the end */
275 /* Return immediately if error */
276 if (hte_check_errors())
281 DPF(D_INFO, "done\n");
283 return hte_check_errors();
287 * Execute a basic single-cache-line memory write/read/verify test using simple
288 * constant pattern, different for READ_TRAIN and WRITE_TRAIN modes.
290 * @mrc_params: host structure for all MRC global data
291 * @addr: memory adress being tested (must hit specific channel/rank)
292 * @first_run: if set then the HTE registers are configured, otherwise it is
293 * assumed configuration is done and we just re-run the test
294 * @mode: READ_TRAIN or WRITE_TRAIN (the difference is in the pattern)
296 * @return: byte lane failure on each bit (for Quark only bit0 and bit1)
298 u16 hte_basic_write_read(struct mrc_params *mrc_params, u32 addr,
299 u8 first_run, u8 mode)
305 /* Enable all error reporting in preparation for HTE test */
306 hte_enable_all_errors();
307 hte_clear_error_regs();
309 errors = hte_basic_data_cmp(mrc_params, addr, first_run, mode);
317 * Examine a single-cache-line memory with write/read/verify test using multiple
318 * data patterns (victim-aggressor algorithm).
320 * @mrc_params: host structure for all MRC global data
321 * @addr: memory adress being tested (must hit specific channel/rank)
322 * @first_run: if set then the HTE registers are configured, otherwise it is
323 * assumed configuration is done and we just re-run the test
325 * @return: byte lane failure on each bit (for Quark only bit0 and bit1)
327 u16 hte_write_stress_bit_lanes(struct mrc_params *mrc_params,
328 u32 addr, u8 first_run)
335 /* Enable all error reporting in preparation for HTE test */
336 hte_enable_all_errors();
337 hte_clear_error_regs();
340 * Loop through each bit in the bytelane.
342 * Each pass creates a victim bit while keeping all other bits the same
343 * as aggressors. AVN HTE adds an auto-rotate feature which allows us
344 * to program the entire victim/aggressor sequence in 1 step.
346 * The victim bit rotates on each pass so no need to have software
347 * implement a victim bit loop like on VLV.
349 errors = hte_rw_data_cmp(mrc_params, addr, HTE_LOOP_CNT,
350 HTE_LFSR_VICTIM_SEED, HTE_LFSR_AGRESSOR_SEED,
351 victim_bit, first_run);
359 * Execute a basic single-cache-line memory write or read.
360 * This is just for receive enable / fine write-levelling purpose.
362 * @addr: memory adress being tested (must hit specific channel/rank)
363 * @first_run: if set then the HTE registers are configured, otherwise it is
364 * assumed configuration is done and we just re-run the test
365 * @is_write: when non-zero memory write operation executed, otherwise read
367 void hte_mem_op(u32 addr, u8 first_run, u8 is_write)
372 hte_enable_all_errors();
373 hte_clear_error_regs();
376 tmp = is_write ? 0x01110021 : 0x01010021;
377 msg_port_write(HTE, 0x00020020, tmp);
379 msg_port_write(HTE, 0x00020021, 0x06000000);
380 msg_port_write(HTE, 0x00020022, addr >> 6);
381 msg_port_write(HTE, 0x00020062, 0x00800015);
382 msg_port_write(HTE, 0x00020063, 0xaaaaaaaa);
383 msg_port_write(HTE, 0x00020064, 0xcccccccc);
384 msg_port_write(HTE, 0x00020065, 0xf0f0f0f0);
385 msg_port_write(HTE, 0x00020061, 0x00030008);
387 for (offset = 0x80; offset <= 0x8f; offset++)
388 msg_port_write(HTE, offset, 0xc33c0000);
391 msg_port_write(HTE, 0x000200a1, 0xffff1000);
392 msg_port_write(HTE, 0x00020011, 0x00011000);
393 msg_port_write(HTE, 0x00020011, 0x00011100);
395 hte_wait_for_complete();