2 * Copyright (C) 2013, Intel Corporation
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
5 * Ported from Intel released Quark UEFI BIOS
6 * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
8 * SPDX-License-Identifier: Intel
14 /* Turn on this macro to enable MRC debugging output */
17 /* MRC Debug Support */
18 #define DPF debug_cond
20 /* debug print type */
23 #define D_ERROR 0x0001
25 #define D_REGRD 0x0004
26 #define D_REGWR 0x0008
27 #define D_FCALL 0x0010
40 #define ENTERFN(...) debug_cond(D_FCALL, "<%s>\n", __func__)
41 #define LEAVEFN(...) debug_cond(D_FCALL, "</%s>\n", __func__)
42 #define REPORTFN(...) debug_cond(D_FCALL, "<%s/>\n", __func__)
44 /* Generic Register Bits */
45 #define BIT0 0x00000001
46 #define BIT1 0x00000002
47 #define BIT2 0x00000004
48 #define BIT3 0x00000008
49 #define BIT4 0x00000010
50 #define BIT5 0x00000020
51 #define BIT6 0x00000040
52 #define BIT7 0x00000080
53 #define BIT8 0x00000100
54 #define BIT9 0x00000200
55 #define BIT10 0x00000400
56 #define BIT11 0x00000800
57 #define BIT12 0x00001000
58 #define BIT13 0x00002000
59 #define BIT14 0x00004000
60 #define BIT15 0x00008000
61 #define BIT16 0x00010000
62 #define BIT17 0x00020000
63 #define BIT18 0x00040000
64 #define BIT19 0x00080000
65 #define BIT20 0x00100000
66 #define BIT21 0x00200000
67 #define BIT22 0x00400000
68 #define BIT23 0x00800000
69 #define BIT24 0x01000000
70 #define BIT25 0x02000000
71 #define BIT26 0x04000000
72 #define BIT27 0x08000000
73 #define BIT28 0x10000000
74 #define BIT29 0x20000000
75 #define BIT30 0x40000000
76 #define BIT31 0x80000000
78 /* Message Bus Port */
80 #define HOST_BRIDGE 0x03
85 /* number of sample points */
87 /* number of PIs to increment per sample */
91 /* indicates to decrease delays when looking for edge */
93 /* indicates to increase delays when looking for edge */
109 void mrc_write_mask(u32 unit, u32 addr, u32 data, u32 mask);
110 void mrc_alt_write_mask(u32 unit, u32 addr, u32 data, u32 mask);
111 void mrc_post_code(uint8_t major, uint8_t minor);
112 void delay_n(uint32_t ns);
113 void delay_u(uint32_t ms);
114 void select_mem_mgr(void);
115 void select_hte(void);
116 void dram_init_command(uint32_t data);
117 void dram_wake_command(void);
118 void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane);
120 void set_rcvn(uint8_t channel, uint8_t rank,
121 uint8_t byte_lane, uint32_t pi_count);
122 uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane);
123 void set_rdqs(uint8_t channel, uint8_t rank,
124 uint8_t byte_lane, uint32_t pi_count);
125 uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
126 void set_wdqs(uint8_t channel, uint8_t rank,
127 uint8_t byte_lane, uint32_t pi_count);
128 uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
129 void set_wdq(uint8_t channel, uint8_t rank,
130 uint8_t byte_lane, uint32_t pi_count);
131 uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane);
132 void set_wcmd(uint8_t channel, uint32_t pi_count);
133 uint32_t get_wcmd(uint8_t channel);
134 void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count);
135 uint32_t get_wclk(uint8_t channel, uint8_t rank);
136 void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count);
137 uint32_t get_wctl(uint8_t channel, uint8_t rank);
138 void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting);
139 uint32_t get_vref(uint8_t channel, uint8_t byte_lane);
141 uint32_t get_addr(uint8_t channel, uint8_t rank);
142 uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel,
143 uint8_t rank, bool rcvn);
144 void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[],
145 uint8_t channel, uint8_t rank, bool rcvn);
146 uint32_t byte_lane_mask(struct mrc_params *mrc_params);
147 uint32_t check_rw_coarse(struct mrc_params *mrc_params, uint32_t address);
148 uint32_t check_bls_ex(struct mrc_params *mrc_params, uint32_t address);
149 void lfsr32(uint32_t *lfsr_ptr);
150 void clear_pointers(void);
151 void print_timings(struct mrc_params *mrc_params);
153 #endif /* _MRC_UTIL_H_ */