2 * Copyright (C) 2013, Intel Corporation
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
5 * Ported from Intel released Quark UEFI BIOS
6 * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
8 * SPDX-License-Identifier: Intel
14 /* System Memory Controller Register Defines */
16 /* Memory Controller Message Bus Registers Offsets */
36 #define DECCSBECNT 0x62
37 #define DECCSBECA 0x68
38 #define DECCSBECS 0x69
39 #define DECCDBECA 0x6A
40 #define DECCDBECS 0x6B
41 #define DFUSESTAT 0x70
46 /* DRAM init command */
47 #define DCMD_MRS1(rnk, dat) (0 | ((rnk) << 22) | (1 << 3) | ((dat) << 6))
48 #define DCMD_REF(rnk) (1 | ((rnk) << 22))
49 #define DCMD_PRE(rnk) (2 | ((rnk) << 22))
50 #define DCMD_PREA(rnk) (2 | ((rnk) << 22) | (BIT10 << 6))
51 #define DCMD_ACT(rnk, row) (3 | ((rnk) << 22) | ((row) << 6))
52 #define DCMD_WR(rnk, col) (4 | ((rnk) << 22) | ((col) << 6))
53 #define DCMD_RD(rnk, col) (5 | ((rnk) << 22) | ((col) << 6))
54 #define DCMD_ZQCS(rnk) (6 | ((rnk) << 22))
55 #define DCMD_ZQCL(rnk) (6 | ((rnk) << 22) | (BIT10 << 6))
56 #define DCMD_NOP(rnk) (7 | ((rnk) << 22))
58 #define DDR3_EMRS1_DIC_40 (0)
59 #define DDR3_EMRS1_DIC_34 (1)
61 #define DDR3_EMRS1_RTTNOM_0 (0)
62 #define DDR3_EMRS1_RTTNOM_60 (0x04)
63 #define DDR3_EMRS1_RTTNOM_120 (0x40)
64 #define DDR3_EMRS1_RTTNOM_40 (0x44)
65 #define DDR3_EMRS1_RTTNOM_20 (0x200)
66 #define DDR3_EMRS1_RTTNOM_30 (0x204)
68 #define DDR3_EMRS2_RTTWR_60 (1 << 9)
69 #define DDR3_EMRS2_RTTWR_120 (1 << 10)
71 /* BEGIN DDRIO Registers */
74 #define DDRIODQ_BL_OFFSET 0x0800
75 #define DDRIODQ_CH_OFFSET ((NUM_BYTE_LANES / 2) * DDRIODQ_BL_OFFSET)
76 #define DDRIOCCC_CH_OFFSET 0x0800
77 #define DDRCOMP_CH_OFFSET 0x0100
80 #define DQOBSCKEBBCTL 0x0000
81 #define DQDLLTXCTL 0x0004
82 #define DQDLLRXCTL 0x0008
83 #define DQMDLLCTL 0x000C
84 #define B0RXIOBUFCTL 0x0010
85 #define B0VREFCTL 0x0014
86 #define B0RXOFFSET1 0x0018
87 #define B0RXOFFSET0 0x001C
88 #define B1RXIOBUFCTL 0x0020
89 #define B1VREFCTL 0x0024
90 #define B1RXOFFSET1 0x0028
91 #define B1RXOFFSET0 0x002C
92 #define DQDFTCTL 0x0030
93 #define DQTRAINSTS 0x0034
94 #define B1DLLPICODER0 0x0038
95 #define B0DLLPICODER0 0x003C
96 #define B1DLLPICODER1 0x0040
97 #define B0DLLPICODER1 0x0044
98 #define B1DLLPICODER2 0x0048
99 #define B0DLLPICODER2 0x004C
100 #define B1DLLPICODER3 0x0050
101 #define B0DLLPICODER3 0x0054
102 #define B1RXDQSPICODE 0x0058
103 #define B0RXDQSPICODE 0x005C
104 #define B1RXDQPICODER32 0x0060
105 #define B1RXDQPICODER10 0x0064
106 #define B0RXDQPICODER32 0x0068
107 #define B0RXDQPICODER10 0x006C
108 #define B01PTRCTL0 0x0070
109 #define B01PTRCTL1 0x0074
110 #define B01DBCTL0 0x0078
111 #define B01DBCTL1 0x007C
112 #define B0LATCTL0 0x0080
113 #define B1LATCTL0 0x0084
114 #define B01LATCTL1 0x0088
115 #define B0ONDURCTL 0x008C
116 #define B1ONDURCTL 0x0090
117 #define B0OVRCTL 0x0094
118 #define B1OVRCTL 0x0098
120 #define B0RK2RKCHGPTRCTRL 0x00A0
121 #define B1RK2RKCHGPTRCTRL 0x00A4
122 #define DQRK2RKCTL 0x00A8
123 #define DQRK2RKPTRCTL 0x00AC
124 #define B0RK2RKLAT 0x00B0
125 #define B1RK2RKLAT 0x00B4
126 #define DQCLKALIGNREG0 0x00B8
127 #define DQCLKALIGNREG1 0x00BC
128 #define DQCLKALIGNREG2 0x00C0
129 #define DQCLKALIGNSTS0 0x00C4
130 #define DQCLKALIGNSTS1 0x00C8
131 #define DQCLKGATE 0x00CC
132 #define B0COMPSLV1 0x00D0
133 #define B1COMPSLV1 0x00D4
134 #define B0COMPSLV2 0x00D8
135 #define B1COMPSLV2 0x00DC
136 #define B0COMPSLV3 0x00E0
137 #define B1COMPSLV3 0x00E4
138 #define DQVISALANECR0TOP 0x00E8
139 #define DQVISALANECR1TOP 0x00EC
140 #define DQVISACONTROLCRTOP 0x00F0
141 #define DQVISALANECR0BL 0x00F4
142 #define DQVISALANECR1BL 0x00F8
143 #define DQVISACONTROLCRBL 0x00FC
144 #define DQTIMINGCTRL 0x010C
147 #define ECCDLLTXCTL 0x2004
148 #define ECCDLLRXCTL 0x2008
149 #define ECCMDLLCTL 0x200C
150 #define ECCB1DLLPICODER0 0x2038
151 #define ECCB1DLLPICODER1 0x2040
152 #define ECCB1DLLPICODER2 0x2048
153 #define ECCB1DLLPICODER3 0x2050
154 #define ECCB01DBCTL0 0x2078
155 #define ECCB01DBCTL1 0x207C
156 #define ECCCLKALIGNREG0 0x20B8
157 #define ECCCLKALIGNREG1 0x20BC
158 #define ECCCLKALIGNREG2 0x20C0
161 #define CMDOBSCKEBBCTL 0x4800
162 #define CMDDLLTXCTL 0x4808
163 #define CMDDLLRXCTL 0x480C
164 #define CMDMDLLCTL 0x4810
165 #define CMDRCOMPODT 0x4814
166 #define CMDDLLPICODER0 0x4820
167 #define CMDDLLPICODER1 0x4824
168 #define CMDCFGREG0 0x4840
169 #define CMDPTRREG 0x4844
170 #define CMDCLKALIGNREG0 0x4850
171 #define CMDCLKALIGNREG1 0x4854
172 #define CMDCLKALIGNREG2 0x4858
173 #define CMDPMCONFIG0 0x485C
174 #define CMDPMDLYREG0 0x4860
175 #define CMDPMDLYREG1 0x4864
176 #define CMDPMDLYREG2 0x4868
177 #define CMDPMDLYREG3 0x486C
178 #define CMDPMDLYREG4 0x4870
179 #define CMDCLKALIGNSTS0 0x4874
180 #define CMDCLKALIGNSTS1 0x4878
181 #define CMDPMSTS0 0x487C
182 #define CMDPMSTS1 0x4880
183 #define CMDCOMPSLV 0x4884
184 #define CMDBONUS0 0x488C
185 #define CMDBONUS1 0x4890
186 #define CMDVISALANECR0 0x4894
187 #define CMDVISALANECR1 0x4898
188 #define CMDVISACONTROLCR 0x489C
189 #define CMDCLKGATE 0x48A0
190 #define CMDTIMINGCTRL 0x48A4
193 #define CCOBSCKEBBCTL 0x5800
194 #define CCRCOMPIO 0x5804
195 #define CCDLLTXCTL 0x5808
196 #define CCDLLRXCTL 0x580C
197 #define CCMDLLCTL 0x5810
198 #define CCRCOMPODT 0x5814
199 #define CCDLLPICODER0 0x5820
200 #define CCDLLPICODER1 0x5824
201 #define CCDDR3RESETCTL 0x5830
202 #define CCCFGREG0 0x5838
203 #define CCCFGREG1 0x5840
204 #define CCPTRREG 0x5844
205 #define CCCLKALIGNREG0 0x5850
206 #define CCCLKALIGNREG1 0x5854
207 #define CCCLKALIGNREG2 0x5858
208 #define CCPMCONFIG0 0x585C
209 #define CCPMDLYREG0 0x5860
210 #define CCPMDLYREG1 0x5864
211 #define CCPMDLYREG2 0x5868
212 #define CCPMDLYREG3 0x586C
213 #define CCPMDLYREG4 0x5870
214 #define CCCLKALIGNSTS0 0x5874
215 #define CCCLKALIGNSTS1 0x5878
216 #define CCPMSTS0 0x587C
217 #define CCPMSTS1 0x5880
218 #define CCCOMPSLV1 0x5884
219 #define CCCOMPSLV2 0x5888
220 #define CCCOMPSLV3 0x588C
221 #define CCBONUS0 0x5894
222 #define CCBONUS1 0x5898
223 #define CCVISALANECR0 0x589C
224 #define CCVISALANECR1 0x58A0
225 #define CCVISACONTROLCR 0x58A4
226 #define CCCLKGATE 0x58A8
227 #define CCTIMINGCTL 0x58AC
230 #define CMPCTRL 0x6800
231 #define SOFTRSTCNTL 0x6804
232 #define MSCNTR 0x6808
233 #define NMSCNTRL 0x680C
234 #define LATCH1CTL 0x6814
235 #define COMPVISALANECR0 0x681C
236 #define COMPVISALANECR1 0x6820
237 #define COMPVISACONTROLCR 0x6824
238 #define COMPBONUS0 0x6830
239 #define TCOCNTCTRL 0x683C
240 #define DQANAODTPUCTL 0x6840
241 #define DQANAODTPDCTL 0x6844
242 #define DQANADRVPUCTL 0x6848
243 #define DQANADRVPDCTL 0x684C
244 #define DQANADLYPUCTL 0x6850
245 #define DQANADLYPDCTL 0x6854
246 #define DQANATCOPUCTL 0x6858
247 #define DQANATCOPDCTL 0x685C
248 #define CMDANADRVPUCTL 0x6868
249 #define CMDANADRVPDCTL 0x686C
250 #define CMDANADLYPUCTL 0x6870
251 #define CMDANADLYPDCTL 0x6874
252 #define CLKANAODTPUCTL 0x6880
253 #define CLKANAODTPDCTL 0x6884
254 #define CLKANADRVPUCTL 0x6888
255 #define CLKANADRVPDCTL 0x688C
256 #define CLKANADLYPUCTL 0x6890
257 #define CLKANADLYPDCTL 0x6894
258 #define CLKANATCOPUCTL 0x6898
259 #define CLKANATCOPDCTL 0x689C
260 #define DQSANAODTPUCTL 0x68A0
261 #define DQSANAODTPDCTL 0x68A4
262 #define DQSANADRVPUCTL 0x68A8
263 #define DQSANADRVPDCTL 0x68AC
264 #define DQSANADLYPUCTL 0x68B0
265 #define DQSANADLYPDCTL 0x68B4
266 #define DQSANATCOPUCTL 0x68B8
267 #define DQSANATCOPDCTL 0x68BC
268 #define CTLANADRVPUCTL 0x68C8
269 #define CTLANADRVPDCTL 0x68CC
270 #define CTLANADLYPUCTL 0x68D0
271 #define CTLANADLYPDCTL 0x68D4
272 #define CHNLBUFSTATIC 0x68F0
273 #define COMPOBSCNTRL 0x68F4
274 #define COMPBUFFDBG0 0x68F8
275 #define COMPBUFFDBG1 0x68FC
276 #define CFGMISCCH0 0x6900
277 #define COMPEN0CH0 0x6904
278 #define COMPEN1CH0 0x6908
279 #define COMPEN2CH0 0x690C
280 #define STATLEGEN0CH0 0x6910
281 #define STATLEGEN1CH0 0x6914
282 #define DQVREFCH0 0x6918
283 #define CMDVREFCH0 0x691C
284 #define CLKVREFCH0 0x6920
285 #define DQSVREFCH0 0x6924
286 #define CTLVREFCH0 0x6928
287 #define TCOVREFCH0 0x692C
288 #define DLYSELCH0 0x6930
289 #define TCODRAMBUFODTCH0 0x6934
290 #define CCBUFODTCH0 0x6938
291 #define RXOFFSETCH0 0x693C
292 #define DQODTPUCTLCH0 0x6940
293 #define DQODTPDCTLCH0 0x6944
294 #define DQDRVPUCTLCH0 0x6948
295 #define DQDRVPDCTLCH0 0x694C
296 #define DQDLYPUCTLCH0 0x6950
297 #define DQDLYPDCTLCH0 0x6954
298 #define DQTCOPUCTLCH0 0x6958
299 #define DQTCOPDCTLCH0 0x695C
300 #define CMDDRVPUCTLCH0 0x6968
301 #define CMDDRVPDCTLCH0 0x696C
302 #define CMDDLYPUCTLCH0 0x6970
303 #define CMDDLYPDCTLCH0 0x6974
304 #define CLKODTPUCTLCH0 0x6980
305 #define CLKODTPDCTLCH0 0x6984
306 #define CLKDRVPUCTLCH0 0x6988
307 #define CLKDRVPDCTLCH0 0x698C
308 #define CLKDLYPUCTLCH0 0x6990
309 #define CLKDLYPDCTLCH0 0x6994
310 #define CLKTCOPUCTLCH0 0x6998
311 #define CLKTCOPDCTLCH0 0x699C
312 #define DQSODTPUCTLCH0 0x69A0
313 #define DQSODTPDCTLCH0 0x69A4
314 #define DQSDRVPUCTLCH0 0x69A8
315 #define DQSDRVPDCTLCH0 0x69AC
316 #define DQSDLYPUCTLCH0 0x69B0
317 #define DQSDLYPDCTLCH0 0x69B4
318 #define DQSTCOPUCTLCH0 0x69B8
319 #define DQSTCOPDCTLCH0 0x69BC
320 #define CTLDRVPUCTLCH0 0x69C8
321 #define CTLDRVPDCTLCH0 0x69CC
322 #define CTLDLYPUCTLCH0 0x69D0
323 #define CTLDLYPDCTLCH0 0x69D4
324 #define FNLUPDTCTLCH0 0x69F0
327 #define MPLLCTRL0 0x7800
328 #define MPLLCTRL1 0x7808
329 #define MPLLCSR0 0x7810
330 #define MPLLCSR1 0x7814
331 #define MPLLCSR2 0x7820
332 #define MPLLDFT 0x7828
333 #define MPLLMON0CTL 0x7830
334 #define MPLLMON1CTL 0x7838
335 #define MPLLMON2CTL 0x783C
336 #define SFRTRIM 0x7850
337 #define MPLLDFTOUT0 0x7858
338 #define MPLLDFTOUT1 0x785C
339 #define MASTERRSTN 0x7880
340 #define PLLLOCKDEL 0x7884
341 #define SFRDEL 0x7888
342 #define CRUVISALANECR0 0x78F0
343 #define CRUVISALANECR1 0x78F4
344 #define CRUVISACONTROLCR 0x78F8
345 #define IOSFVISALANECR0 0x78FC
346 #define IOSFVISALANECR1 0x7900
347 #define IOSFVISACONTROLCR 0x7904
349 /* END DDRIO Registers */
351 /* DRAM Specific Message Bus OpCodes */
352 #define MSG_OP_DRAM_INIT 0x68
353 #define MSG_OP_DRAM_WAKE 0xCA
355 #define SAMPLE_SIZE 6
357 /* must be less than this number to enable early deadband */
358 #define EARLY_DB 0x12
359 /* must be greater than this number to enable late deadband */
362 #define CHX_REGS (11 * 4)
367 #define MCEIL(num, den) ((uint8_t)((num + den - 1) / den))
368 #define MMAX(a, b) ((a) > (b) ? (a) : (b))
369 #define DEAD_LOOP() for (;;);
371 #define MIN_RDQS_EYE 10 /* in PI Codes */
372 #define MIN_VREF_EYE 10 /* in VREF Codes */
373 /* how many RDQS codes to jump while margining */
375 /* how many VREF codes to jump while margining */
377 /* offset into "vref_codes[]" for minimum allowed VREF setting */
378 #define VREF_MIN 0x00
379 /* offset into "vref_codes[]" for maximum allowed VREF setting */
380 #define VREF_MAX 0x3F
381 #define RDQS_MIN 0x00 /* minimum RDQS delay value */
382 #define RDQS_MAX 0x3F /* maximum RDQS delay value */
384 /* how many WDQ codes to jump while margining */
399 /* enable STATIC timing settings for RCVN (BACKUP_MODE) */
401 /* enable STATIC timing settings for WDQS (BACKUP_MODE) */
403 /* enable STATIC timing settings for RDQS (BACKUP_MODE) */
405 /* enable STATIC timing settings for WDQ (BACKUP_MODE) */
407 /* enable *COMP overrides (BACKUP_MODE) */
409 /* enable the RD_TRAIN eye check */
412 /* enable Host to Memory Clock Alignment */
414 /* enable multi-rank support via rank2rank sharing */
416 /* disable signals not used in 16bit mode of DDRIO */
417 #define FORCE_16BIT_DDRIO
419 #define PLATFORM_ID 1
421 void clear_self_refresh(struct mrc_params *mrc_params);
422 void prog_ddr_timing_control(struct mrc_params *mrc_params);
423 void prog_decode_before_jedec(struct mrc_params *mrc_params);
424 void perform_ddr_reset(struct mrc_params *mrc_params);
425 void ddrphy_init(struct mrc_params *mrc_params);
426 void perform_jedec_init(struct mrc_params *mrc_params);
427 void set_ddr_init_complete(struct mrc_params *mrc_params);
428 void restore_timings(struct mrc_params *mrc_params);
429 void default_timings(struct mrc_params *mrc_params);
430 void rcvn_cal(struct mrc_params *mrc_params);
431 void wr_level(struct mrc_params *mrc_params);
432 void prog_page_ctrl(struct mrc_params *mrc_params);
433 void rd_train(struct mrc_params *mrc_params);
434 void wr_train(struct mrc_params *mrc_params);
435 void store_timings(struct mrc_params *mrc_params);
436 void enable_scrambling(struct mrc_params *mrc_params);
437 void prog_ddr_control(struct mrc_params *mrc_params);
438 void prog_dra_drb(struct mrc_params *mrc_params);
439 void perform_wake(struct mrc_params *mrc_params);
440 void change_refresh_period(struct mrc_params *mrc_params);
441 void set_auto_refresh(struct mrc_params *mrc_params);
442 void ecc_enable(struct mrc_params *mrc_params);
443 void memory_test(struct mrc_params *mrc_params);
444 void lock_registers(struct mrc_params *mrc_params);