git.sur5r.net Git - u-boot/blob - arch/x86/cpu/queensbay/irq.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
   4  * Copyright (C) 2015 Google, Inc
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <asm/io.h>
  10 #include <asm/irq.h>
  11 #include <asm/pci.h>
  12 #include <asm/arch/device.h>
  13 #include <asm/arch/tnc.h>
  14
  15 int queensbay_irq_router_probe(struct udevice *dev)
  16 {
  17         struct tnc_rcba *rcba;
  18         u32 base;
  19
  20         dm_pci_read_config32(dev->parent, LPC_RCBA, &base);
  21         base &= ~MEM_BAR_EN;
  22         rcba = (struct tnc_rcba *)base;
  23
  24         /* Make sure all internal PCI devices are using INTA */
  25         writel(INTA, &rcba->d02ip);
  26         writel(INTA, &rcba->d03ip);
  27         writel(INTA, &rcba->d27ip);
  28         writel(INTA, &rcba->d31ip);
  29         writel(INTA, &rcba->d23ip);
  30         writel(INTA, &rcba->d24ip);
  31         writel(INTA, &rcba->d25ip);
  32         writel(INTA, &rcba->d26ip);
  33
  34         /*
  35          * Route TunnelCreek PCI device interrupt pin to PIRQ
  36          *
  37          * Since PCIe downstream ports received INTx are routed to PIRQ
  38          * A/B/C/D directly and not configurable, we have to route PCIe
  39          * root ports' INTx to PIRQ A/B/C/D as well. For other devices
  40          * on TunneCreek, route them to PIRQ E/F/G/H.
  41          */
  42         writew(PIRQE, &rcba->d02ir);
  43         writew(PIRQF, &rcba->d03ir);
  44         writew(PIRQG, &rcba->d27ir);
  45         writew(PIRQH, &rcba->d31ir);
  46         writew(PIRQA, &rcba->d23ir);
  47         writew(PIRQB, &rcba->d24ir);
  48         writew(PIRQC, &rcba->d25ir);
  49         writew(PIRQD, &rcba->d26ir);
  50
  51         return irq_router_common_init(dev);
  52 }
  53
  54 static const struct udevice_id queensbay_irq_router_ids[] = {
  55         { .compatible = "intel,queensbay-irq-router" },
  56         { }
  57 };
  58
  59 U_BOOT_DRIVER(queensbay_irq_router_drv) = {
  60         .name           = "queensbay_intel_irq",
  61         .id             = UCLASS_IRQ,
  62         .of_match       = queensbay_irq_router_ids,
  63         .probe          = queensbay_irq_router_probe,
  64 };