2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/device.h>
13 #include <asm/arch/tnc.h>
14 #include <asm/fsp/fsp_support.h>
15 #include <asm/processor.h>
17 static void unprotect_spi_flash(void)
21 bc = x86_pci_read_config32(TNC_LPC, 0xd8);
22 bc |= 0x1; /* unprotect the flash */
23 x86_pci_write_config32(TNC_LPC, 0xd8, bc);
26 int arch_cpu_init(void)
28 struct pci_controller *hose;
31 post_code(POST_CPU_INIT);
32 #ifdef CONFIG_SYS_X86_TSC_TIMER
33 timer_set_base(rdtsc());
36 ret = x86_cpu_init_f();
40 ret = pci_early_init_hose(&hose);
44 unprotect_spi_flash();
49 void cpu_irq_init(void)
51 struct tnc_rcba *rcba;
54 base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
56 rcba = (struct tnc_rcba *)base;
58 /* Make sure all internal PCI devices are using INTA */
59 writel(INTA, &rcba->d02ip);
60 writel(INTA, &rcba->d03ip);
61 writel(INTA, &rcba->d27ip);
62 writel(INTA, &rcba->d31ip);
63 writel(INTA, &rcba->d23ip);
64 writel(INTA, &rcba->d24ip);
65 writel(INTA, &rcba->d25ip);
66 writel(INTA, &rcba->d26ip);
69 * Route TunnelCreek PCI device interrupt pin to PIRQ
71 * Since PCIe downstream ports received INTx are routed to PIRQ
72 * A/B/C/D directly and not configurable, we route internal PCI
73 * device's INTx to PIRQ E/F/G/H.
75 writew(PIRQE, &rcba->d02ir);
76 writew(PIRQF, &rcba->d03ir);
77 writew(PIRQG, &rcba->d27ir);
78 writew(PIRQH, &rcba->d31ir);
79 writew(PIRQE, &rcba->d23ir);
80 writew(PIRQF, &rcba->d24ir);
81 writew(PIRQG, &rcba->d25ir);
82 writew(PIRQH, &rcba->d26ir);
85 int arch_misc_init(void)