2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/device.h>
13 #include <asm/arch/tnc.h>
14 #include <asm/fsp/fsp_support.h>
15 #include <asm/processor.h>
17 static void unprotect_spi_flash(void)
21 bc = x86_pci_read_config32(TNC_LPC, 0xd8);
22 bc |= 0x1; /* unprotect the flash */
23 x86_pci_write_config32(TNC_LPC, 0xd8, bc);
26 static void __maybe_unused disable_igd(void)
29 * According to Atom E6xx datasheet, setting VGA Disable (bit17)
30 * of Graphics Controller register (offset 0x50) prevents IGD
31 * (D2:F0) from reporting itself as a VGA display controller
32 * class in the PCI configuration space, and should also prevent
33 * it from responding to VGA legacy memory range and I/O addresses.
35 * However test result shows that with just VGA Disable bit set and
36 * a PCIe graphics card connected to one of the PCIe controllers on
37 * the E6xx, accessing the VGA legacy space still causes system hang.
38 * After a number of attempts, it turns out besides VGA Disable bit,
39 * the SDVO (D3:F0) device should be disabled to make it work.
41 * To simplify, use the Function Disable register (offset 0xc4)
42 * to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these
43 * two devices will be completely disabled (invisible in the PCI
44 * configuration space) unless a system reset is performed.
46 x86_pci_write_config32(TNC_IGD, IGD_FD, FUNC_DISABLE);
47 x86_pci_write_config32(TNC_SDVO, IGD_FD, FUNC_DISABLE);
50 int arch_cpu_init(void)
54 post_code(POST_CPU_INIT);
56 ret = x86_cpu_init_f();
63 int arch_early_init_r(void)
65 #ifdef CONFIG_DISABLE_IGD
72 void cpu_irq_init(void)
74 struct tnc_rcba *rcba;
77 base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
79 rcba = (struct tnc_rcba *)base;
81 /* Make sure all internal PCI devices are using INTA */
82 writel(INTA, &rcba->d02ip);
83 writel(INTA, &rcba->d03ip);
84 writel(INTA, &rcba->d27ip);
85 writel(INTA, &rcba->d31ip);
86 writel(INTA, &rcba->d23ip);
87 writel(INTA, &rcba->d24ip);
88 writel(INTA, &rcba->d25ip);
89 writel(INTA, &rcba->d26ip);
92 * Route TunnelCreek PCI device interrupt pin to PIRQ
94 * Since PCIe downstream ports received INTx are routed to PIRQ
95 * A/B/C/D directly and not configurable, we have to route PCIe
96 * root ports' INTx to PIRQ A/B/C/D as well. For other devices
97 * on TunneCreek, route them to PIRQ E/F/G/H.
99 writew(PIRQE, &rcba->d02ir);
100 writew(PIRQF, &rcba->d03ir);
101 writew(PIRQG, &rcba->d27ir);
102 writew(PIRQH, &rcba->d31ir);
103 writew(PIRQA, &rcba->d23ir);
104 writew(PIRQB, &rcba->d24ir);
105 writew(PIRQC, &rcba->d25ir);
106 writew(PIRQD, &rcba->d26ir);
109 int arch_misc_init(void)
111 unprotect_spi_flash();