2 * (C) Copyright 2008-2011
3 * Graeme Russ, <graeme.russ@gmail.com>
6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/arch/pci.h>
32 #include <asm/arch/sc520.h>
39 { SC520_IRQ0, 0, 0x01 },
40 { SC520_IRQ1, 0, 0x02 },
41 { SC520_IRQ2, 1, 0x02 },
42 { SC520_IRQ3, 0, 0x08 },
43 { SC520_IRQ4, 0, 0x10 },
44 { SC520_IRQ5, 0, 0x20 },
45 { SC520_IRQ6, 0, 0x40 },
46 { SC520_IRQ7, 0, 0x80 },
48 { SC520_IRQ8, 1, 0x01 },
49 { SC520_IRQ9, 1, 0x02 },
50 { SC520_IRQ10, 1, 0x04 },
51 { SC520_IRQ11, 1, 0x08 },
52 { SC520_IRQ12, 1, 0x10 },
53 { SC520_IRQ13, 1, 0x20 },
54 { SC520_IRQ14, 1, 0x40 },
55 { SC520_IRQ15, 1, 0x80 }
58 /* The interrupt used for PCI INTA-INTD */
59 int sc520_pci_ints[15] = {
60 -1, -1, -1, -1, -1, -1, -1, -1,
61 -1, -1, -1, -1, -1, -1, -1
64 /* utility function to configure a pci interrupt */
65 int pci_sc520_set_irq(int pci_pin, int irq)
71 debug("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
73 if (irq < 0 || irq > 15)
74 return -1; /* illegal irq */
76 if (pci_pin < 0 || pci_pin > 15)
77 return -1; /* illegal pci int pin */
79 /* first disable any non-pci interrupt source that use
82 /* PCI interrupt mapping (A through D)*/
83 for (i = 0; i <= 3 ; i++) {
84 tmpb = readb(&sc520_mmcr->pci_int_map[i]);
86 if (tmpb == sc520_irq[irq].priority)
87 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]);
90 /* GP IRQ interrupt mapping */
91 for (i = 0; i <= 10 ; i++) {
92 tmpb = readb(&sc520_mmcr->gp_int_map[i]);
94 if (tmpb == sc520_irq[irq].priority)
95 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]);
98 /* Set the trigger to level */
99 tmpb = readb(&sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
100 tmpb |= sc520_irq[irq].level_bit;
101 writeb(tmpb, &sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
106 /* route the interrupt */
107 writeb(sc520_irq[irq].priority,
108 &sc520_mmcr->pci_int_map[pci_pin]);
110 /* GPIRQ0-GPIRQ10 used for additional PCI INTS */
111 writeb(sc520_irq[irq].priority,
112 &sc520_mmcr->gp_int_map[pci_pin - 4]);
114 /* also set the polarity in this case */
115 tmpw = readw(&sc520_mmcr->intpinpol);
116 tmpw |= (1 << (pci_pin-4));
117 writew(tmpw, &sc520_mmcr->intpinpol);
120 /* register the pin */
121 sc520_pci_ints[pci_pin] = irq;
127 void pci_sc520_init(struct pci_controller *hose)
129 hose->first_busno = 0;
130 hose->last_busno = 0xff;
131 hose->region_count = pci_set_regions(hose);
133 pci_setup_type1(hose,
137 pci_register_hose(hose);
139 hose->last_busno = pci_hose_scan(hose);
141 /* enable target memory acceses on host brige */
142 pci_write_config_word(0, PCI_COMMAND,
143 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);