git.sur5r.net Git - u-boot/blob - arch/x86/dts/bayleybay.dts

   1 /*
   2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/gpio/x86-gpio.h>
  10 #include <dt-bindings/interrupt-router/intel-irq.h>
  11
  12 /include/ "skeleton.dtsi"
  13 /include/ "keyboard.dtsi"
  14 /include/ "serial.dtsi"
  15 /include/ "rtc.dtsi"
  16 /include/ "tsc_timer.dtsi"
  17
  18 / {
  19         model = "Intel Bayley Bay";
  20         compatible = "intel,bayleybay", "intel,baytrail";
  21
  22         aliases {
  23                 serial0 = &serial;
  24                 spi0 = &spi;
  25         };
  26
  27         config {
  28                 silent_console = <0>;
  29         };
  30
  31         chosen {
  32                 stdout-path = "/serial";
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 cpu@0 {
  40                         device_type = "cpu";
  41                         compatible = "intel,baytrail-cpu";
  42                         reg = <0>;
  43                         intel,apic-id = <0>;
  44                 };
  45
  46                 cpu@1 {
  47                         device_type = "cpu";
  48                         compatible = "intel,baytrail-cpu";
  49                         reg = <1>;
  50                         intel,apic-id = <2>;
  51                 };
  52
  53                 cpu@2 {
  54                         device_type = "cpu";
  55                         compatible = "intel,baytrail-cpu";
  56                         reg = <2>;
  57                         intel,apic-id = <4>;
  58                 };
  59
  60                 cpu@3 {
  61                         device_type = "cpu";
  62                         compatible = "intel,baytrail-cpu";
  63                         reg = <3>;
  64                         intel,apic-id = <6>;
  65                 };
  66         };
  67
  68         pci {
  69                 compatible = "pci-x86";
  70                 #address-cells = <3>;
  71                 #size-cells = <2>;
  72                 u-boot,dm-pre-reloc;
  73                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
  74                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
  75                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  76
  77                 pch@1f,0 {
  78                         reg = <0x0000f800 0 0 0 0>;
  79                         compatible = "intel,pch9";
  80                         #address-cells = <1>;
  81                         #size-cells = <1>;
  82
  83                         irq-router {
  84                                 compatible = "intel,irq-router";
  85                                 intel,pirq-config = "ibase";
  86                                 intel,ibase-offset = <0x50>;
  87                                 intel,pirq-link = <8 8>;
  88                                 intel,pirq-mask = <0xdee0>;
  89                                 intel,pirq-routing = <
  90                                         /* BayTrail PCI devices */
  91                                         PCI_BDF(0, 2, 0) INTA PIRQA
  92                                         PCI_BDF(0, 3, 0) INTA PIRQA
  93                                         PCI_BDF(0, 16, 0) INTA PIRQA
  94                                         PCI_BDF(0, 17, 0) INTA PIRQA
  95                                         PCI_BDF(0, 18, 0) INTA PIRQA
  96                                         PCI_BDF(0, 19, 0) INTA PIRQA
  97                                         PCI_BDF(0, 20, 0) INTA PIRQA
  98                                         PCI_BDF(0, 21, 0) INTA PIRQA
  99                                         PCI_BDF(0, 22, 0) INTA PIRQA
 100                                         PCI_BDF(0, 23, 0) INTA PIRQA
 101                                         PCI_BDF(0, 24, 0) INTA PIRQA
 102                                         PCI_BDF(0, 24, 1) INTC PIRQC
 103                                         PCI_BDF(0, 24, 2) INTD PIRQD
 104                                         PCI_BDF(0, 24, 3) INTB PIRQB
 105                                         PCI_BDF(0, 24, 4) INTA PIRQA
 106                                         PCI_BDF(0, 24, 5) INTC PIRQC
 107                                         PCI_BDF(0, 24, 6) INTD PIRQD
 108                                         PCI_BDF(0, 24, 7) INTB PIRQB
 109                                         PCI_BDF(0, 26, 0) INTA PIRQA
 110                                         PCI_BDF(0, 27, 0) INTA PIRQA
 111                                         PCI_BDF(0, 28, 0) INTA PIRQA
 112                                         PCI_BDF(0, 28, 1) INTB PIRQB
 113                                         PCI_BDF(0, 28, 2) INTC PIRQC
 114                                         PCI_BDF(0, 28, 3) INTD PIRQD
 115                                         PCI_BDF(0, 29, 0) INTA PIRQA
 116                                         PCI_BDF(0, 30, 0) INTA PIRQA
 117                                         PCI_BDF(0, 30, 1) INTD PIRQD
 118                                         PCI_BDF(0, 30, 2) INTB PIRQB
 119                                         PCI_BDF(0, 30, 3) INTC PIRQC
 120                                         PCI_BDF(0, 30, 4) INTD PIRQD
 121                                         PCI_BDF(0, 30, 5) INTB PIRQB
 122                                         PCI_BDF(0, 31, 3) INTB PIRQB
 123
 124                                         /*
 125                                          * PCIe root ports downstream
 126                                          * interrupts
 127                                          */
 128                                         PCI_BDF(1, 0, 0) INTA PIRQA
 129                                         PCI_BDF(1, 0, 0) INTB PIRQB
 130                                         PCI_BDF(1, 0, 0) INTC PIRQC
 131                                         PCI_BDF(1, 0, 0) INTD PIRQD
 132                                         PCI_BDF(2, 0, 0) INTA PIRQB
 133                                         PCI_BDF(2, 0, 0) INTB PIRQC
 134                                         PCI_BDF(2, 0, 0) INTC PIRQD
 135                                         PCI_BDF(2, 0, 0) INTD PIRQA
 136                                         PCI_BDF(3, 0, 0) INTA PIRQC
 137                                         PCI_BDF(3, 0, 0) INTB PIRQD
 138                                         PCI_BDF(3, 0, 0) INTC PIRQA
 139                                         PCI_BDF(3, 0, 0) INTD PIRQB
 140                                         PCI_BDF(4, 0, 0) INTA PIRQD
 141                                         PCI_BDF(4, 0, 0) INTB PIRQA
 142                                         PCI_BDF(4, 0, 0) INTC PIRQB
 143                                         PCI_BDF(4, 0, 0) INTD PIRQC
 144                                 >;
 145                         };
 146
 147                         spi: spi {
 148                                 #address-cells = <1>;
 149                                 #size-cells = <0>;
 150                                 compatible = "intel,ich9-spi";
 151                                 spi-flash@0 {
 152                                         #address-cells = <1>;
 153                                         #size-cells = <1>;
 154                                         reg = <0>;
 155                                         compatible = "winbond,w25q64dw",
 156                                                 "spi-flash";
 157                                         memory-map = <0xff800000 0x00800000>;
 158                                         rw-mrc-cache {
 159                                                 label = "rw-mrc-cache";
 160                                                 reg = <0x006e0000 0x00010000>;
 161                                         };
 162                                 };
 163                         };
 164
 165                         gpioa {
 166                                 compatible = "intel,ich6-gpio";
 167                                 u-boot,dm-pre-reloc;
 168                                 reg = <0 0x20>;
 169                                 bank-name = "A";
 170                         };
 171
 172                         gpiob {
 173                                 compatible = "intel,ich6-gpio";
 174                                 u-boot,dm-pre-reloc;
 175                                 reg = <0x20 0x20>;
 176                                 bank-name = "B";
 177                         };
 178
 179                         gpioc {
 180                                 compatible = "intel,ich6-gpio";
 181                                 u-boot,dm-pre-reloc;
 182                                 reg = <0x40 0x20>;
 183                                 bank-name = "C";
 184                         };
 185
 186                         gpiod {
 187                                 compatible = "intel,ich6-gpio";
 188                                 u-boot,dm-pre-reloc;
 189                                 reg = <0x60 0x20>;
 190                                 bank-name = "D";
 191                         };
 192
 193                         gpioe {
 194                                 compatible = "intel,ich6-gpio";
 195                                 u-boot,dm-pre-reloc;
 196                                 reg = <0x80 0x20>;
 197                                 bank-name = "E";
 198                         };
 199
 200                         gpiof {
 201                                 compatible = "intel,ich6-gpio";
 202                                 u-boot,dm-pre-reloc;
 203                                 reg = <0xA0 0x20>;
 204                                 bank-name = "F";
 205                         };
 206                 };
 207         };
 208
 209         fsp {
 210                 compatible = "intel,baytrail-fsp";
 211                 fsp,mrc-init-tseg-size = <0>;
 212                 fsp,mrc-init-mmio-size = <0x800>;
 213                 fsp,mrc-init-spd-addr1 = <0xa0>;
 214                 fsp,mrc-init-spd-addr2 = <0xa2>;
 215                 fsp,emmc-boot-mode = <2>;
 216                 fsp,enable-sdio;
 217                 fsp,enable-sdcard;
 218                 fsp,enable-hsuart1;
 219                 fsp,enable-spi;
 220                 fsp,enable-sata;
 221                 fsp,sata-mode = <1>;
 222                 fsp,enable-lpe;
 223                 fsp,lpss-sio-enable-pci-mode;
 224                 fsp,enable-dma0;
 225                 fsp,enable-dma1;
 226                 fsp,enable-i2c0;
 227                 fsp,enable-i2c1;
 228                 fsp,enable-i2c2;
 229                 fsp,enable-i2c3;
 230                 fsp,enable-i2c4;
 231                 fsp,enable-i2c5;
 232                 fsp,enable-i2c6;
 233                 fsp,enable-pwm0;
 234                 fsp,enable-pwm1;
 235                 fsp,igd-dvmt50-pre-alloc = <2>;
 236                 fsp,aperture-size = <2>;
 237                 fsp,gtt-size = <2>;
 238                 fsp,serial-debug-port-address = <0x3f8>;
 239                 fsp,serial-debug-port-type = <1>;
 240                 fsp,scc-enable-pci-mode;
 241                 fsp,os-selection = <4>;
 242                 fsp,emmc45-ddr50-enabled;
 243                 fsp,emmc45-retune-timer-value = <8>;
 244                 fsp,enable-igd;
 245         };
 246
 247         microcode {
 248                 update@0 {
 249 #include "microcode/m0230671117.dtsi"
 250                 };
 251                 update@1 {
 252 #include "microcode/m0130673322.dtsi"
 253                 };
 254                 update@2 {
 255 #include "microcode/m0130679901.dtsi"
 256                 };
 257         };
 258
 259 };