2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <dt-bindings/gpio/x86-gpio.h>
10 #include <dt-bindings/interrupt-router/intel-irq.h>
12 /include/ "skeleton.dtsi"
13 /include/ "serial.dtsi"
17 model = "Intel Bayley Bay";
18 compatible = "intel,bayleybay", "intel,baytrail";
30 stdout-path = "/serial";
39 compatible = "intel,baytrail-cpu";
46 compatible = "intel,baytrail-cpu";
53 compatible = "intel,baytrail-cpu";
60 compatible = "intel,baytrail-cpu";
69 compatible = "intel,ich-spi";
74 compatible = "winbond,w25q64dw", "spi-flash";
75 memory-map = <0xff800000 0x00800000>;
77 label = "rw-mrc-cache";
78 reg = <0x006e0000 0x00010000>;
84 compatible = "intel,ich6-gpio";
91 compatible = "intel,ich6-gpio";
98 compatible = "intel,ich6-gpio";
105 compatible = "intel,ich6-gpio";
112 compatible = "intel,ich6-gpio";
119 compatible = "intel,ich6-gpio";
126 compatible = "pci-x86";
127 #address-cells = <3>;
130 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
131 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
132 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
135 reg = <0x0000f800 0 0 0 0>;
136 compatible = "intel,irq-router";
137 intel,pirq-config = "ibase";
138 intel,ibase-offset = <0x50>;
139 intel,pirq-link = <8 8>;
140 intel,pirq-mask = <0xdee0>;
141 intel,pirq-routing = <
142 /* BayTrail PCI devices */
143 PCI_BDF(0, 2, 0) INTA PIRQA
144 PCI_BDF(0, 3, 0) INTA PIRQA
145 PCI_BDF(0, 16, 0) INTA PIRQA
146 PCI_BDF(0, 17, 0) INTA PIRQA
147 PCI_BDF(0, 18, 0) INTA PIRQA
148 PCI_BDF(0, 19, 0) INTA PIRQA
149 PCI_BDF(0, 20, 0) INTA PIRQA
150 PCI_BDF(0, 21, 0) INTA PIRQA
151 PCI_BDF(0, 22, 0) INTA PIRQA
152 PCI_BDF(0, 23, 0) INTA PIRQA
153 PCI_BDF(0, 24, 0) INTA PIRQA
154 PCI_BDF(0, 24, 1) INTC PIRQC
155 PCI_BDF(0, 24, 2) INTD PIRQD
156 PCI_BDF(0, 24, 3) INTB PIRQB
157 PCI_BDF(0, 24, 4) INTA PIRQA
158 PCI_BDF(0, 24, 5) INTC PIRQC
159 PCI_BDF(0, 24, 6) INTD PIRQD
160 PCI_BDF(0, 24, 7) INTB PIRQB
161 PCI_BDF(0, 26, 0) INTA PIRQA
162 PCI_BDF(0, 27, 0) INTA PIRQA
163 PCI_BDF(0, 28, 0) INTA PIRQA
164 PCI_BDF(0, 28, 1) INTB PIRQB
165 PCI_BDF(0, 28, 2) INTC PIRQC
166 PCI_BDF(0, 28, 3) INTD PIRQD
167 PCI_BDF(0, 29, 0) INTA PIRQA
168 PCI_BDF(0, 30, 0) INTA PIRQA
169 PCI_BDF(0, 30, 1) INTD PIRQD
170 PCI_BDF(0, 30, 2) INTB PIRQB
171 PCI_BDF(0, 30, 3) INTC PIRQC
172 PCI_BDF(0, 30, 4) INTD PIRQD
173 PCI_BDF(0, 30, 5) INTB PIRQB
174 PCI_BDF(0, 31, 3) INTB PIRQB
176 /* PCIe root ports downstream interrupts */
177 PCI_BDF(1, 0, 0) INTA PIRQA
178 PCI_BDF(1, 0, 0) INTB PIRQB
179 PCI_BDF(1, 0, 0) INTC PIRQC
180 PCI_BDF(1, 0, 0) INTD PIRQD
181 PCI_BDF(2, 0, 0) INTA PIRQB
182 PCI_BDF(2, 0, 0) INTB PIRQC
183 PCI_BDF(2, 0, 0) INTC PIRQD
184 PCI_BDF(2, 0, 0) INTD PIRQA
185 PCI_BDF(3, 0, 0) INTA PIRQC
186 PCI_BDF(3, 0, 0) INTB PIRQD
187 PCI_BDF(3, 0, 0) INTC PIRQA
188 PCI_BDF(3, 0, 0) INTD PIRQB
189 PCI_BDF(4, 0, 0) INTA PIRQD
190 PCI_BDF(4, 0, 0) INTB PIRQA
191 PCI_BDF(4, 0, 0) INTC PIRQB
192 PCI_BDF(4, 0, 0) INTD PIRQC
198 compatible = "intel,baytrail-fsp";
199 fsp,mrc-init-tseg-size = <0>;
200 fsp,mrc-init-mmio-size = <0x800>;
201 fsp,mrc-init-spd-addr1 = <0xa0>;
202 fsp,mrc-init-spd-addr2 = <0xa2>;
203 fsp,emmc-boot-mode = <2>;
211 fsp,lpss-sio-enable-pci-mode;
223 fsp,igd-dvmt50-pre-alloc = <2>;
224 fsp,aperture-size = <2>;
226 fsp,serial-debug-port-address = <0x3f8>;
227 fsp,serial-debug-port-type = <1>;
228 fsp,scc-enable-pci-mode;
229 fsp,os-selection = <4>;
230 fsp,emmc45-ddr50-enabled;
231 fsp,emmc45-retune-timer-value = <8>;
237 #include "microcode/m0230671117.dtsi"
240 #include "microcode/m0130673322.dtsi"
243 #include "microcode/m0130679901.dtsi"