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[u-boot] / arch / x86 / dts / baytrail_som-db5800-som-6867.dts
1 /*
2  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3  * Copyright (C) 2016, George McCollister <george.mccollister@gmail.com>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 /dts-v1/;
9
10 #include <dt-bindings/gpio/x86-gpio.h>
11 #include <dt-bindings/interrupt-router/intel-irq.h>
12
13 /include/ "skeleton.dtsi"
14 /include/ "serial.dtsi"
15 /include/ "rtc.dtsi"
16 /include/ "tsc_timer.dtsi"
17
18 / {
19         model = "Advantech SOM-DB5800-SOM-6867";
20         compatible = "advantech,som-db5800-som-6867", "intel,baytrail";
21
22         aliases {
23                 serial0 = &serial;
24                 spi0 = &spi;
25         };
26
27         config {
28                 silent_console = <0>;
29         };
30
31         pch_pinctrl {
32                 compatible = "intel,x86-pinctrl";
33                 reg = <0 0>;
34
35                 /* HDA_RSTB */
36                 soc_gpio_s0_8@0 {
37                         pad-offset = <0x220>;
38                         mode-func = <2>;
39                 };
40
41                 /* HDA_SYNC */
42                 soc_gpio_s0_9@0 {
43                         pad-offset = <0x250>;
44                         mode-func = <2>;
45                         pull-assign = <1>;
46                 };
47
48                 /* HDA_CLK */
49                 soc_gpio_s0_10@0 {
50                         pad-offset = <0x240>;
51                         mode-func = <2>;
52                 };
53
54                 /* HDA_SDO */
55                 soc_gpio_s0_11@0 {
56                         pad-offset = <0x260>;
57                         mode-func = <2>;
58                         pull-assign = <1>;
59                 };
60
61                 /* HDA_SDI0 */
62                 soc_gpio_s0_12@0 {
63                         pad-offset = <0x270>;
64                         mode-func = <2>;
65                 };
66         };
67
68         chosen {
69                 stdout-path = "/serial";
70         };
71
72         cpus {
73                 #address-cells = <1>;
74                 #size-cells = <0>;
75
76                 cpu@0 {
77                         device_type = "cpu";
78                         compatible = "intel,baytrail-cpu";
79                         reg = <0>;
80                         intel,apic-id = <0>;
81                 };
82
83                 cpu@1 {
84                         device_type = "cpu";
85                         compatible = "intel,baytrail-cpu";
86                         reg = <1>;
87                         intel,apic-id = <2>;
88                 };
89
90                 cpu@2 {
91                         device_type = "cpu";
92                         compatible = "intel,baytrail-cpu";
93                         reg = <2>;
94                         intel,apic-id = <4>;
95                 };
96
97                 cpu@3 {
98                         device_type = "cpu";
99                         compatible = "intel,baytrail-cpu";
100                         reg = <3>;
101                         intel,apic-id = <6>;
102                 };
103
104         };
105
106         pci {
107                 compatible = "intel,pci-baytrail", "pci-x86";
108                 #address-cells = <3>;
109                 #size-cells = <2>;
110                 u-boot,dm-pre-reloc;
111                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
112                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
113                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
114
115                 pch@1f,0 {
116                         reg = <0x0000f800 0 0 0 0>;
117                         compatible = "pci8086,0f1c", "intel,pch9";
118                         #address-cells = <1>;
119                         #size-cells = <1>;
120
121                         irq-router {
122                                 compatible = "intel,irq-router";
123                                 intel,pirq-config = "ibase";
124                                 intel,ibase-offset = <0x50>;
125                                 intel,actl-addr = <0>;
126                                 intel,pirq-link = <8 8>;
127                                 intel,pirq-mask = <0xdee0>;
128                                 intel,pirq-routing = <
129                                         /* BayTrail PCI devices */
130                                         PCI_BDF(0, 2, 0) INTA PIRQA
131                                         PCI_BDF(0, 3, 0) INTA PIRQA
132                                         PCI_BDF(0, 16, 0) INTA PIRQA
133                                         PCI_BDF(0, 17, 0) INTA PIRQA
134                                         PCI_BDF(0, 18, 0) INTA PIRQA
135                                         PCI_BDF(0, 19, 0) INTA PIRQA
136                                         PCI_BDF(0, 20, 0) INTA PIRQA
137                                         PCI_BDF(0, 21, 0) INTA PIRQA
138                                         PCI_BDF(0, 22, 0) INTA PIRQA
139                                         PCI_BDF(0, 23, 0) INTA PIRQA
140                                         PCI_BDF(0, 24, 0) INTA PIRQA
141                                         PCI_BDF(0, 24, 1) INTC PIRQC
142                                         PCI_BDF(0, 24, 2) INTD PIRQD
143                                         PCI_BDF(0, 24, 3) INTB PIRQB
144                                         PCI_BDF(0, 24, 4) INTA PIRQA
145                                         PCI_BDF(0, 24, 5) INTC PIRQC
146                                         PCI_BDF(0, 24, 6) INTD PIRQD
147                                         PCI_BDF(0, 24, 7) INTB PIRQB
148                                         PCI_BDF(0, 26, 0) INTA PIRQA
149                                         PCI_BDF(0, 27, 0) INTA PIRQA
150                                         PCI_BDF(0, 28, 0) INTA PIRQA
151                                         PCI_BDF(0, 28, 1) INTB PIRQB
152                                         PCI_BDF(0, 28, 2) INTC PIRQC
153                                         PCI_BDF(0, 28, 3) INTD PIRQD
154                                         PCI_BDF(0, 29, 0) INTA PIRQA
155                                         PCI_BDF(0, 30, 0) INTA PIRQA
156                                         PCI_BDF(0, 30, 1) INTD PIRQD
157                                         PCI_BDF(0, 30, 2) INTB PIRQB
158                                         PCI_BDF(0, 30, 3) INTC PIRQC
159                                         PCI_BDF(0, 30, 4) INTD PIRQD
160                                         PCI_BDF(0, 30, 5) INTB PIRQB
161                                         PCI_BDF(0, 31, 3) INTB PIRQB
162
163                                         /*
164                                          * PCIe root ports downstream
165                                          * interrupts
166                                          */
167                                         PCI_BDF(1, 0, 0) INTA PIRQA
168                                         PCI_BDF(1, 0, 0) INTB PIRQB
169                                         PCI_BDF(1, 0, 0) INTC PIRQC
170                                         PCI_BDF(1, 0, 0) INTD PIRQD
171                                         PCI_BDF(2, 0, 0) INTA PIRQB
172                                         PCI_BDF(2, 0, 0) INTB PIRQC
173                                         PCI_BDF(2, 0, 0) INTC PIRQD
174                                         PCI_BDF(2, 0, 0) INTD PIRQA
175                                         PCI_BDF(3, 0, 0) INTA PIRQC
176                                         PCI_BDF(3, 0, 0) INTB PIRQD
177                                         PCI_BDF(3, 0, 0) INTC PIRQA
178                                         PCI_BDF(3, 0, 0) INTD PIRQB
179                                         PCI_BDF(4, 0, 0) INTA PIRQD
180                                         PCI_BDF(4, 0, 0) INTB PIRQA
181                                         PCI_BDF(4, 0, 0) INTC PIRQB
182                                         PCI_BDF(4, 0, 0) INTD PIRQC
183                                 >;
184                         };
185
186                         spi: spi {
187                                 #address-cells = <1>;
188                                 #size-cells = <0>;
189                                 compatible = "intel,ich9-spi";
190                                 spi-flash@0 {
191                                         #address-cells = <1>;
192                                         #size-cells = <1>;
193                                         reg = <0>;
194                                         compatible = "macronix,mx25l6405d",
195                                                 "spi-flash";
196                                         memory-map = <0xff800000 0x00800000>;
197                                         rw-mrc-cache {
198                                                 label = "rw-mrc-cache";
199                                                 reg = <0x006f0000 0x00010000>;
200                                         };
201                                 };
202                         };
203
204                         gpioa {
205                                 compatible = "intel,ich6-gpio";
206                                 u-boot,dm-pre-reloc;
207                                 reg = <0 0x20>;
208                                 bank-name = "A";
209                         };
210
211                         gpiob {
212                                 compatible = "intel,ich6-gpio";
213                                 u-boot,dm-pre-reloc;
214                                 reg = <0x20 0x20>;
215                                 bank-name = "B";
216                         };
217
218                         gpioc {
219                                 compatible = "intel,ich6-gpio";
220                                 u-boot,dm-pre-reloc;
221                                 reg = <0x40 0x20>;
222                                 bank-name = "C";
223                         };
224
225                         gpiod {
226                                 compatible = "intel,ich6-gpio";
227                                 u-boot,dm-pre-reloc;
228                                 reg = <0x60 0x20>;
229                                 bank-name = "D";
230                         };
231
232                         gpioe {
233                                 compatible = "intel,ich6-gpio";
234                                 u-boot,dm-pre-reloc;
235                                 reg = <0x80 0x20>;
236                                 bank-name = "E";
237                         };
238
239                         gpiof {
240                                 compatible = "intel,ich6-gpio";
241                                 u-boot,dm-pre-reloc;
242                                 reg = <0xA0 0x20>;
243                                 bank-name = "F";
244                         };
245                 };
246         };
247
248         fsp {
249                 compatible = "intel,baytrail-fsp";
250                 fsp,mrc-init-tseg-size = <0>;
251                 fsp,mrc-init-mmio-size = <0x800>;
252                 fsp,mrc-init-spd-addr1 = <0xa0>;
253                 fsp,mrc-init-spd-addr2 = <0xa2>;
254                 fsp,enable-spi;
255                 fsp,enable-sata;
256                 fsp,sata-mode = <1>;
257                 fsp,enable-azalia;
258                 fsp,lpss-sio-enable-pci-mode;
259                 fsp,enable-dma0;
260                 fsp,enable-dma1;
261                 fsp,enable-i2c0;
262                 fsp,enable-i2c1;
263                 fsp,enable-i2c2;
264                 fsp,enable-i2c3;
265                 fsp,enable-i2c4;
266                 fsp,enable-i2c5;
267                 fsp,enable-i2c6;
268                 fsp,enable-pwm0;
269                 fsp,enable-pwm1;
270                 fsp,igd-dvmt50-pre-alloc = <2>;
271                 fsp,aperture-size = <2>;
272                 fsp,gtt-size = <2>;
273                 fsp,scc-enable-pci-mode;
274                 fsp,os-selection = <4>;
275                 fsp,enable-igd;
276                 fsp,serial-debug-port-address = <0x3f8>;
277                 fsp,serial-debug-port-type = <1>;
278         };
279
280         microcode {
281                 update@0 {
282 #include "microcode/m0130673325.dtsi"
283                 };
284                 update@1 {
285 #include "microcode/m0130679907.dtsi"
286                 };
287         };
288
289 };