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x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode
[u-boot] / arch / x86 / dts / baytrail_som-db5800-som-6867.dts
1 /*
2  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3  * Copyright (C) 2016, George McCollister <george.mccollister@gmail.com>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 /dts-v1/;
9
10 #include <dt-bindings/gpio/x86-gpio.h>
11 #include <dt-bindings/interrupt-router/intel-irq.h>
12
13 /include/ "skeleton.dtsi"
14 /include/ "serial.dtsi"
15 /include/ "rtc.dtsi"
16 /include/ "tsc_timer.dtsi"
17
18 / {
19         model = "Advantech SOM-DB5800-SOM-6867";
20         compatible = "advantech,som-db5800-som-6867", "intel,baytrail";
21
22         aliases {
23                 serial0 = &serial;
24                 spi0 = &spi;
25         };
26
27         config {
28                 silent_console = <0>;
29         };
30
31         pch_pinctrl {
32                 compatible = "intel,x86-pinctrl";
33                 reg = <0 0>;
34
35                 /* HDA_RSTB */
36                 soc_gpio_s0_8@0 {
37                         pad-offset = <0x220>;
38                         mode-func = <2>;
39                 };
40
41                 /* HDA_SYNC */
42                 soc_gpio_s0_9@0 {
43                         pad-offset = <0x250>;
44                         mode-func = <2>;
45                         pull-assign = <1>;
46                 };
47
48                 /* HDA_CLK */
49                 soc_gpio_s0_10@0 {
50                         pad-offset = <0x240>;
51                         mode-func = <2>;
52                 };
53
54                 /* HDA_SDO */
55                 soc_gpio_s0_11@0 {
56                         pad-offset = <0x260>;
57                         mode-func = <2>;
58                         pull-assign = <1>;
59                 };
60
61                 /* HDA_SDI0 */
62                 soc_gpio_s0_12@0 {
63                         pad-offset = <0x270>;
64                         mode-func = <2>;
65                 };
66
67                 /* SERIRQ */
68                 soc_gpio_s0_50@0 {
69                         pad-offset = <0x560>;
70                         mode-func = <1>;
71                 };
72         };
73
74         chosen {
75                 stdout-path = "/serial";
76         };
77
78         cpus {
79                 #address-cells = <1>;
80                 #size-cells = <0>;
81
82                 cpu@0 {
83                         device_type = "cpu";
84                         compatible = "intel,baytrail-cpu";
85                         reg = <0>;
86                         intel,apic-id = <0>;
87                 };
88
89                 cpu@1 {
90                         device_type = "cpu";
91                         compatible = "intel,baytrail-cpu";
92                         reg = <1>;
93                         intel,apic-id = <2>;
94                 };
95
96                 cpu@2 {
97                         device_type = "cpu";
98                         compatible = "intel,baytrail-cpu";
99                         reg = <2>;
100                         intel,apic-id = <4>;
101                 };
102
103                 cpu@3 {
104                         device_type = "cpu";
105                         compatible = "intel,baytrail-cpu";
106                         reg = <3>;
107                         intel,apic-id = <6>;
108                 };
109
110         };
111
112         pci {
113                 compatible = "intel,pci-baytrail", "pci-x86";
114                 #address-cells = <3>;
115                 #size-cells = <2>;
116                 u-boot,dm-pre-reloc;
117                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
118                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
119                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
120
121                 pch@1f,0 {
122                         reg = <0x0000f800 0 0 0 0>;
123                         compatible = "pci8086,0f1c", "intel,pch9";
124                         #address-cells = <1>;
125                         #size-cells = <1>;
126
127                         irq-router {
128                                 compatible = "intel,irq-router";
129                                 intel,pirq-config = "ibase";
130                                 intel,ibase-offset = <0x50>;
131                                 intel,actl-addr = <0>;
132                                 intel,pirq-link = <8 8>;
133                                 intel,pirq-mask = <0xdee0>;
134                                 intel,pirq-routing = <
135                                         /* BayTrail PCI devices */
136                                         PCI_BDF(0, 2, 0) INTA PIRQA
137                                         PCI_BDF(0, 3, 0) INTA PIRQA
138                                         PCI_BDF(0, 16, 0) INTA PIRQA
139                                         PCI_BDF(0, 17, 0) INTA PIRQA
140                                         PCI_BDF(0, 18, 0) INTA PIRQA
141                                         PCI_BDF(0, 19, 0) INTA PIRQA
142                                         PCI_BDF(0, 20, 0) INTA PIRQA
143                                         PCI_BDF(0, 21, 0) INTA PIRQA
144                                         PCI_BDF(0, 22, 0) INTA PIRQA
145                                         PCI_BDF(0, 23, 0) INTA PIRQA
146                                         PCI_BDF(0, 24, 0) INTA PIRQA
147                                         PCI_BDF(0, 24, 1) INTC PIRQC
148                                         PCI_BDF(0, 24, 2) INTD PIRQD
149                                         PCI_BDF(0, 24, 3) INTB PIRQB
150                                         PCI_BDF(0, 24, 4) INTA PIRQA
151                                         PCI_BDF(0, 24, 5) INTC PIRQC
152                                         PCI_BDF(0, 24, 6) INTD PIRQD
153                                         PCI_BDF(0, 24, 7) INTB PIRQB
154                                         PCI_BDF(0, 26, 0) INTA PIRQA
155                                         PCI_BDF(0, 27, 0) INTA PIRQA
156                                         PCI_BDF(0, 28, 0) INTA PIRQA
157                                         PCI_BDF(0, 28, 1) INTB PIRQB
158                                         PCI_BDF(0, 28, 2) INTC PIRQC
159                                         PCI_BDF(0, 28, 3) INTD PIRQD
160                                         PCI_BDF(0, 29, 0) INTA PIRQA
161                                         PCI_BDF(0, 30, 0) INTA PIRQA
162                                         PCI_BDF(0, 30, 1) INTD PIRQD
163                                         PCI_BDF(0, 30, 2) INTB PIRQB
164                                         PCI_BDF(0, 30, 3) INTC PIRQC
165                                         PCI_BDF(0, 30, 4) INTD PIRQD
166                                         PCI_BDF(0, 30, 5) INTB PIRQB
167                                         PCI_BDF(0, 31, 3) INTB PIRQB
168
169                                         /*
170                                          * PCIe root ports downstream
171                                          * interrupts
172                                          */
173                                         PCI_BDF(1, 0, 0) INTA PIRQA
174                                         PCI_BDF(1, 0, 0) INTB PIRQB
175                                         PCI_BDF(1, 0, 0) INTC PIRQC
176                                         PCI_BDF(1, 0, 0) INTD PIRQD
177                                         PCI_BDF(2, 0, 0) INTA PIRQB
178                                         PCI_BDF(2, 0, 0) INTB PIRQC
179                                         PCI_BDF(2, 0, 0) INTC PIRQD
180                                         PCI_BDF(2, 0, 0) INTD PIRQA
181                                         PCI_BDF(3, 0, 0) INTA PIRQC
182                                         PCI_BDF(3, 0, 0) INTB PIRQD
183                                         PCI_BDF(3, 0, 0) INTC PIRQA
184                                         PCI_BDF(3, 0, 0) INTD PIRQB
185                                         PCI_BDF(4, 0, 0) INTA PIRQD
186                                         PCI_BDF(4, 0, 0) INTB PIRQA
187                                         PCI_BDF(4, 0, 0) INTC PIRQB
188                                         PCI_BDF(4, 0, 0) INTD PIRQC
189                                 >;
190                         };
191
192                         spi: spi {
193                                 #address-cells = <1>;
194                                 #size-cells = <0>;
195                                 compatible = "intel,ich9-spi";
196                                 spi-flash@0 {
197                                         #address-cells = <1>;
198                                         #size-cells = <1>;
199                                         reg = <0>;
200                                         compatible = "macronix,mx25l6405d",
201                                                 "spi-flash";
202                                         memory-map = <0xff800000 0x00800000>;
203                                         rw-mrc-cache {
204                                                 label = "rw-mrc-cache";
205                                                 reg = <0x006f0000 0x00010000>;
206                                         };
207                                 };
208                         };
209
210                         gpioa {
211                                 compatible = "intel,ich6-gpio";
212                                 u-boot,dm-pre-reloc;
213                                 reg = <0 0x20>;
214                                 bank-name = "A";
215                                 use-lvl-write-cache;
216                         };
217
218                         gpiob {
219                                 compatible = "intel,ich6-gpio";
220                                 u-boot,dm-pre-reloc;
221                                 reg = <0x20 0x20>;
222                                 bank-name = "B";
223                                 use-lvl-write-cache;
224                         };
225
226                         gpioc {
227                                 compatible = "intel,ich6-gpio";
228                                 u-boot,dm-pre-reloc;
229                                 reg = <0x40 0x20>;
230                                 bank-name = "C";
231                                 use-lvl-write-cache;
232                         };
233
234                         gpiod {
235                                 compatible = "intel,ich6-gpio";
236                                 u-boot,dm-pre-reloc;
237                                 reg = <0x60 0x20>;
238                                 bank-name = "D";
239                                 use-lvl-write-cache;
240                         };
241
242                         gpioe {
243                                 compatible = "intel,ich6-gpio";
244                                 u-boot,dm-pre-reloc;
245                                 reg = <0x80 0x20>;
246                                 bank-name = "E";
247                                 use-lvl-write-cache;
248                         };
249
250                         gpiof {
251                                 compatible = "intel,ich6-gpio";
252                                 u-boot,dm-pre-reloc;
253                                 reg = <0xA0 0x20>;
254                                 bank-name = "F";
255                                 use-lvl-write-cache;
256                         };
257                 };
258         };
259
260         fsp {
261                 compatible = "intel,baytrail-fsp";
262                 fsp,mrc-init-tseg-size = <0>;
263                 fsp,mrc-init-mmio-size = <0x800>;
264                 fsp,mrc-init-spd-addr1 = <0xa0>;
265                 fsp,mrc-init-spd-addr2 = <0xa2>;
266                 fsp,enable-spi;
267                 fsp,enable-sata;
268                 fsp,sata-mode = <1>;
269                 fsp,enable-azalia;
270                 fsp,lpss-sio-enable-pci-mode;
271                 fsp,enable-dma0;
272                 fsp,enable-dma1;
273                 fsp,enable-i2c0;
274                 fsp,enable-i2c1;
275                 fsp,enable-i2c2;
276                 fsp,enable-i2c3;
277                 fsp,enable-i2c4;
278                 fsp,enable-i2c5;
279                 fsp,enable-i2c6;
280                 fsp,enable-pwm0;
281                 fsp,enable-pwm1;
282                 fsp,igd-dvmt50-pre-alloc = <2>;
283                 fsp,aperture-size = <2>;
284                 fsp,gtt-size = <2>;
285                 fsp,scc-enable-pci-mode;
286                 fsp,os-selection = <4>;
287                 fsp,enable-igd;
288                 fsp,serial-debug-port-address = <0x3f8>;
289                 fsp,serial-debug-port-type = <1>;
290         };
291
292         microcode {
293                 update@0 {
294 #include "microcode/m0130673325.dtsi"
295                 };
296                 update@1 {
297 #include "microcode/m0130679907.dtsi"
298                 };
299         };
300
301 };