git.sur5r.net Git - u-boot/blob - arch/x86/dts/cherryhill.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <asm/arch-braswell/fsp/fsp_configs.h>
   9 #include <dt-bindings/interrupt-router/intel-irq.h>
  10
  11 /include/ "skeleton.dtsi"
  12 /include/ "serial.dtsi"
  13 /include/ "rtc.dtsi"
  14 /include/ "tsc_timer.dtsi"
  15
  16 / {
  17         model = "Intel Cherry Hill";
  18         compatible = "intel,cherryhill", "intel,braswell";
  19
  20         aliases {
  21                 serial0 = &serial;
  22                 spi0 = &spi;
  23         };
  24
  25         config {
  26                 silent_console = <0>;
  27         };
  28
  29         chosen {
  30                 stdout-path = "/serial";
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 cpu@0 {
  38                         device_type = "cpu";
  39                         compatible = "cpu-x86";
  40                         reg = <0>;
  41                         intel,apic-id = <0>;
  42                 };
  43
  44                 cpu@1 {
  45                         device_type = "cpu";
  46                         compatible = "cpu-x86";
  47                         reg = <1>;
  48                         intel,apic-id = <2>;
  49                 };
  50
  51                 cpu@2 {
  52                         device_type = "cpu";
  53                         compatible = "cpu-x86";
  54                         reg = <2>;
  55                         intel,apic-id = <4>;
  56                 };
  57
  58                 cpu@3 {
  59                         device_type = "cpu";
  60                         compatible = "cpu-x86";
  61                         reg = <3>;
  62                         intel,apic-id = <6>;
  63                 };
  64         };
  65
  66         pci {
  67                 compatible = "pci-x86";
  68                 #address-cells = <3>;
  69                 #size-cells = <2>;
  70                 u-boot,dm-pre-reloc;
  71                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
  72                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
  73                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  74
  75                 pch@1f,0 {
  76                         reg = <0x0000f800 0 0 0 0>;
  77                         compatible = "intel,pch9";
  78
  79                         irq-router {
  80                                 compatible = "intel,irq-router";
  81                                 intel,pirq-config = "ibase";
  82                                 intel,ibase-offset = <0x50>;
  83                                 intel,pirq-link = <8 8>;
  84                                 intel,pirq-mask = <0xdee0>;
  85                                 intel,pirq-routing = <
  86                                         /* Braswell PCI devices */
  87                                         PCI_BDF(0, 2, 0) INTA PIRQA
  88                                         PCI_BDF(0, 3, 0) INTA PIRQA
  89                                         PCI_BDF(0, 11, 0) INTA PIRQA
  90                                         PCI_BDF(0, 16, 0) INTA PIRQA
  91                                         PCI_BDF(0, 17, 0) INTA PIRQA
  92                                         PCI_BDF(0, 18, 0) INTA PIRQA
  93                                         PCI_BDF(0, 19, 0) INTA PIRQA
  94                                         PCI_BDF(0, 20, 0) INTA PIRQA
  95                                         PCI_BDF(0, 21, 0) INTA PIRQA
  96                                         PCI_BDF(0, 24, 0) INTA PIRQA
  97                                         PCI_BDF(0, 24, 1) INTC PIRQC
  98                                         PCI_BDF(0, 24, 2) INTD PIRQD
  99                                         PCI_BDF(0, 24, 3) INTB PIRQB
 100                                         PCI_BDF(0, 24, 4) INTA PIRQA
 101                                         PCI_BDF(0, 24, 5) INTC PIRQC
 102                                         PCI_BDF(0, 24, 6) INTD PIRQD
 103                                         PCI_BDF(0, 24, 7) INTB PIRQB
 104                                         PCI_BDF(0, 26, 0) INTA PIRQA
 105                                         PCI_BDF(0, 27, 0) INTA PIRQA
 106                                         PCI_BDF(0, 28, 0) INTA PIRQA
 107                                         PCI_BDF(0, 28, 1) INTB PIRQB
 108                                         PCI_BDF(0, 28, 2) INTC PIRQC
 109                                         PCI_BDF(0, 28, 3) INTD PIRQD
 110                                         PCI_BDF(0, 30, 0) INTA PIRQA
 111                                         PCI_BDF(0, 30, 3) INTA PIRQA
 112                                         PCI_BDF(0, 30, 4) INTA PIRQA
 113                                         PCI_BDF(0, 31, 0) INTB PIRQB
 114                                         PCI_BDF(0, 31, 3) INTB PIRQB
 115
 116                                         /*
 117                                          * PCIe root ports downstream
 118                                          * interrupts
 119                                          */
 120                                         PCI_BDF(1, 0, 0) INTA PIRQA
 121                                         PCI_BDF(1, 0, 0) INTB PIRQB
 122                                         PCI_BDF(1, 0, 0) INTC PIRQC
 123                                         PCI_BDF(1, 0, 0) INTD PIRQD
 124                                         PCI_BDF(2, 0, 0) INTA PIRQB
 125                                         PCI_BDF(2, 0, 0) INTB PIRQC
 126                                         PCI_BDF(2, 0, 0) INTC PIRQD
 127                                         PCI_BDF(2, 0, 0) INTD PIRQA
 128                                         PCI_BDF(3, 0, 0) INTA PIRQC
 129                                         PCI_BDF(3, 0, 0) INTB PIRQD
 130                                         PCI_BDF(3, 0, 0) INTC PIRQA
 131                                         PCI_BDF(3, 0, 0) INTD PIRQB
 132                                         PCI_BDF(4, 0, 0) INTA PIRQD
 133                                         PCI_BDF(4, 0, 0) INTB PIRQA
 134                                         PCI_BDF(4, 0, 0) INTC PIRQB
 135                                         PCI_BDF(4, 0, 0) INTD PIRQC
 136                                 >;
 137                         };
 138
 139                         spi: spi {
 140                                 #address-cells = <1>;
 141                                 #size-cells = <0>;
 142                                 compatible = "intel,ich9-spi";
 143                                 intel,spi-lock-down;
 144
 145                                 spi-flash@0 {
 146                                         #address-cells = <1>;
 147                                         #size-cells = <1>;
 148                                         reg = <0>;
 149                                         compatible = "macronix,mx25u6435f", "spi-flash";
 150                                         memory-map = <0xff800000 0x00800000>;
 151                                         rw-mrc-cache {
 152                                                 label = "rw-mrc-cache";
 153                                                 reg = <0x005e0000 0x00010000>;
 154                                         };
 155                                 };
 156                         };
 157                 };
 158         };
 159
 160         fsp {
 161                 compatible = "intel,braswell-fsp";
 162                 fsp,memory-upd {
 163                         compatible = "intel,braswell-fsp-memory";
 164                         fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_4MB>;
 165                         fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
 166                         fsp,mrc-init-spd-addr1 = <0xa0>;
 167                         fsp,mrc-init-spd-addr2 = <0xa2>;
 168                         fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_32MB>;
 169                         fsp,aperture-size = <APERTURE_SIZE_256MB>;
 170                         fsp,gtt-size = <GTT_SIZE_1MB>;
 171                         fsp,enable-dvfs;
 172                         fsp,memory-type = <DRAM_TYPE_DDR3>;
 173                 };
 174                 fsp,silicon-upd {
 175                         compatible = "intel,braswell-fsp-silicon";
 176                         fsp,sdcard-mode = <SDCARD_MODE_PCI>;
 177                         fsp,enable-hsuart1;
 178                         fsp,enable-sata;
 179                         fsp,enable-xhci;
 180                         fsp,lpe-mode = <LPE_MODE_PCI>;
 181                         fsp,enable-dma0;
 182                         fsp,enable-dma1;
 183                         fsp,enable-i2c0;
 184                         fsp,enable-i2c1;
 185                         fsp,enable-i2c2;
 186                         fsp,enable-i2c3;
 187                         fsp,enable-i2c4;
 188                         fsp,enable-i2c5;
 189                         fsp,enable-i2c6;
 190                         fsp,emmc-mode = <EMMC_MODE_PCI>;
 191                         fsp,sata-speed = <SATA_SPEED_GEN3>;
 192                         fsp,pmic-i2c-bus = <0>;
 193                         fsp,enable-isp;
 194                         fsp,isp-pci-dev-config = <ISP_PCI_DEV_CONFIG_2>;
 195                         fsp,pnp-settings = <PNP_SETTING_POWER_AND_PERF>;
 196                         fsp,sd-detect-chk;
 197                 };
 198         };
 199
 200         microcode {
 201                 update@0 {
 202 #include "microcode/m01406c2220.dtsi"
 203                 };
 204                 update@1 {
 205 #include "microcode/m01406c3363.dtsi"
 206                 };
 207                 update@2 {
 208 #include "microcode/m01406c440a.dtsi"
 209                 };
 210         };
 211
 212 };