1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
8 #include <asm/arch-braswell/fsp/fsp_configs.h>
9 #include <dt-bindings/interrupt-router/intel-irq.h>
11 /include/ "skeleton.dtsi"
12 /include/ "serial.dtsi"
14 /include/ "tsc_timer.dtsi"
17 model = "Intel Cherry Hill";
18 compatible = "intel,cherryhill", "intel,braswell";
30 stdout-path = "/serial";
39 compatible = "cpu-x86";
46 compatible = "cpu-x86";
53 compatible = "cpu-x86";
60 compatible = "cpu-x86";
67 compatible = "pci-x86";
71 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
72 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
73 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
76 reg = <0x0000f800 0 0 0 0>;
77 compatible = "intel,pch9";
82 compatible = "intel,irq-router";
83 intel,pirq-config = "ibase";
84 intel,ibase-offset = <0x50>;
85 intel,pirq-link = <8 8>;
86 intel,pirq-mask = <0xdee0>;
87 intel,pirq-routing = <
88 /* Braswell PCI devices */
89 PCI_BDF(0, 2, 0) INTA PIRQA
90 PCI_BDF(0, 3, 0) INTA PIRQA
91 PCI_BDF(0, 11, 0) INTA PIRQA
92 PCI_BDF(0, 16, 0) INTA PIRQA
93 PCI_BDF(0, 17, 0) INTA PIRQA
94 PCI_BDF(0, 18, 0) INTA PIRQA
95 PCI_BDF(0, 19, 0) INTA PIRQA
96 PCI_BDF(0, 20, 0) INTA PIRQA
97 PCI_BDF(0, 21, 0) INTA PIRQA
98 PCI_BDF(0, 24, 0) INTA PIRQA
99 PCI_BDF(0, 24, 1) INTC PIRQC
100 PCI_BDF(0, 24, 2) INTD PIRQD
101 PCI_BDF(0, 24, 3) INTB PIRQB
102 PCI_BDF(0, 24, 4) INTA PIRQA
103 PCI_BDF(0, 24, 5) INTC PIRQC
104 PCI_BDF(0, 24, 6) INTD PIRQD
105 PCI_BDF(0, 24, 7) INTB PIRQB
106 PCI_BDF(0, 26, 0) INTA PIRQA
107 PCI_BDF(0, 27, 0) INTA PIRQA
108 PCI_BDF(0, 28, 0) INTA PIRQA
109 PCI_BDF(0, 28, 1) INTB PIRQB
110 PCI_BDF(0, 28, 2) INTC PIRQC
111 PCI_BDF(0, 28, 3) INTD PIRQD
112 PCI_BDF(0, 30, 0) INTA PIRQA
113 PCI_BDF(0, 30, 3) INTA PIRQA
114 PCI_BDF(0, 30, 4) INTA PIRQA
115 PCI_BDF(0, 31, 0) INTB PIRQB
116 PCI_BDF(0, 31, 3) INTB PIRQB
119 * PCIe root ports downstream
122 PCI_BDF(1, 0, 0) INTA PIRQA
123 PCI_BDF(1, 0, 0) INTB PIRQB
124 PCI_BDF(1, 0, 0) INTC PIRQC
125 PCI_BDF(1, 0, 0) INTD PIRQD
126 PCI_BDF(2, 0, 0) INTA PIRQB
127 PCI_BDF(2, 0, 0) INTB PIRQC
128 PCI_BDF(2, 0, 0) INTC PIRQD
129 PCI_BDF(2, 0, 0) INTD PIRQA
130 PCI_BDF(3, 0, 0) INTA PIRQC
131 PCI_BDF(3, 0, 0) INTB PIRQD
132 PCI_BDF(3, 0, 0) INTC PIRQA
133 PCI_BDF(3, 0, 0) INTD PIRQB
134 PCI_BDF(4, 0, 0) INTA PIRQD
135 PCI_BDF(4, 0, 0) INTB PIRQA
136 PCI_BDF(4, 0, 0) INTC PIRQB
137 PCI_BDF(4, 0, 0) INTD PIRQC
142 #address-cells = <1>;
144 compatible = "intel,ich9-spi";
148 #address-cells = <1>;
151 compatible = "macronix,mx25u6435f", "spi-flash";
152 memory-map = <0xff800000 0x00800000>;
154 label = "rw-mrc-cache";
155 reg = <0x005e0000 0x00010000>;
163 compatible = "intel,braswell-fsp";
165 compatible = "intel,braswell-fsp-memory";
166 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_4MB>;
167 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
168 fsp,mrc-init-spd-addr1 = <0xa0>;
169 fsp,mrc-init-spd-addr2 = <0xa2>;
170 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_32MB>;
171 fsp,aperture-size = <APERTURE_SIZE_256MB>;
172 fsp,gtt-size = <GTT_SIZE_1MB>;
174 fsp,memory-type = <DRAM_TYPE_DDR3>;
177 compatible = "intel,braswell-fsp-silicon";
178 fsp,sdcard-mode = <SDCARD_MODE_PCI>;
182 fsp,lpe-mode = <LPE_MODE_PCI>;
192 fsp,emmc-mode = <EMMC_MODE_PCI>;
193 fsp,sata-speed = <SATA_SPEED_GEN3>;
194 fsp,pmic-i2c-bus = <0>;
196 fsp,isp-pci-dev-config = <ISP_PCI_DEV_CONFIG_2>;
197 fsp,pnp-settings = <PNP_SETTING_POWER_AND_PERF>;
204 #include "microcode/m01406c2220.dtsi"
207 #include "microcode/m01406c3363.dtsi"
210 #include "microcode/m01406c440a.dtsi"