git.sur5r.net Git - u-boot/blob - arch/x86/dts/chromebox_panther.dts

   1 /dts-v1/;
   2
   3 /include/ "skeleton.dtsi"
   4 /include/ "serial.dtsi"
   5 /include/ "rtc.dtsi"
   6 /include/ "tsc_timer.dtsi"
   7
   8 / {
   9         model = "Google Panther";
  10         compatible = "google,panther", "intel,haswell";
  11
  12         aliases {
  13                 spi0 = &spi;
  14         };
  15
  16         config {
  17                 silent-console = <0>;
  18                 no-keyboard;
  19         };
  20
  21         chosen {
  22                 stdout-path = "/serial";
  23         };
  24
  25         pci {
  26                 compatible = "pci-x86";
  27                 #address-cells = <3>;
  28                 #size-cells = <2>;
  29                 u-boot,dm-pre-reloc;
  30                 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
  31                         0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
  32                         0x01000000 0x0 0x1000 0x1000 0 0xf000>;
  33
  34                 pch@1f,0 {
  35                         reg = <0x0000f800 0 0 0 0>;
  36                         compatible = "intel,pch9";
  37                         #address-cells = <1>;
  38                         #size-cells = <1>;
  39
  40                         spi: spi {
  41                                 #address-cells = <1>;
  42                                 #size-cells = <0>;
  43                                 compatible = "intel,ich9-spi";
  44                                 spi-flash@0 {
  45                                         #size-cells = <1>;
  46                                         #address-cells = <1>;
  47                                         reg = <0>;
  48                                         compatible = "winbond,w25q64",
  49                                                 "spi-flash";
  50                                         memory-map = <0xff800000 0x00800000>;
  51                                         rw-mrc-cache {
  52                                                 label = "rw-mrc-cache";
  53                                                 reg = <0x003e0000 0x00010000>;
  54                                         };
  55                                 };
  56                         };
  57
  58                         gpioa {
  59                                 compatible = "intel,ich6-gpio";
  60                                 u-boot,dm-pre-reloc;
  61                                 reg = <0 0x10>;
  62                                 bank-name = "A";
  63                         };
  64
  65                         gpiob {
  66                                 compatible = "intel,ich6-gpio";
  67                                 u-boot,dm-pre-reloc;
  68                                 reg = <0x30 0x10>;
  69                                 bank-name = "B";
  70                         };
  71
  72                         gpioc {
  73                                 compatible = "intel,ich6-gpio";
  74                                 u-boot,dm-pre-reloc;
  75                                 reg = <0x40 0x10>;
  76                                 bank-name = "C";
  77                         };
  78                 };
  79         };
  80
  81         tpm {
  82                 reg = <0xfed40000 0x5000>;
  83                 compatible = "infineon,slb9635lpc";
  84         };
  85
  86 };