git.sur5r.net Git - u-boot/blob - arch/x86/dts/chromebox_panther.dts

   1 /dts-v1/;
   2
   3 /include/ "skeleton.dtsi"
   4 /include/ "serial.dtsi"
   5 /include/ "rtc.dtsi"
   6 /include/ "tsc_timer.dtsi"
   7
   8 / {
   9         model = "Google Panther";
  10         compatible = "google,panther", "intel,haswell";
  11
  12         aliases {
  13                 spi0 = "/spi";
  14         };
  15
  16         config {
  17                 silent-console = <0>;
  18                 no-keyboard;
  19         };
  20
  21         gpioa {
  22                 compatible = "intel,ich6-gpio";
  23                 u-boot,dm-pre-reloc;
  24                 reg = <0 0x10>;
  25                 bank-name = "A";
  26         };
  27
  28         gpiob {
  29                 compatible = "intel,ich6-gpio";
  30                 u-boot,dm-pre-reloc;
  31                 reg = <0x30 0x10>;
  32                 bank-name = "B";
  33         };
  34
  35         gpioc {
  36                 compatible = "intel,ich6-gpio";
  37                 u-boot,dm-pre-reloc;
  38                 reg = <0x40 0x10>;
  39                 bank-name = "C";
  40         };
  41
  42         chosen {
  43                 stdout-path = "/serial";
  44         };
  45
  46         pci {
  47                 compatible = "pci-x86";
  48                 #address-cells = <3>;
  49                 #size-cells = <2>;
  50                 u-boot,dm-pre-reloc;
  51                 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
  52                         0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
  53                         0x01000000 0x0 0x1000 0x1000 0 0xf000>;
  54         };
  55
  56         spi {
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59                 compatible = "intel,ich-spi";
  60                 spi-flash@0 {
  61                         #size-cells = <1>;
  62                         #address-cells = <1>;
  63                         reg = <0>;
  64                         compatible = "winbond,w25q64", "spi-flash";
  65                         memory-map = <0xff800000 0x00800000>;
  66                         rw-mrc-cache {
  67                                 label = "rw-mrc-cache";
  68                                 reg = <0x003e0000 0x00010000>;
  69                         };
  70                 };
  71         };
  72
  73         tpm {
  74                 reg = <0xfed40000 0x5000>;
  75                 compatible = "infineon,slb9635lpc";
  76         };
  77
  78 };