2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch-baytrail/fsp/fsp_configs.h>
11 #include <dt-bindings/gpio/x86-gpio.h>
12 #include <dt-bindings/interrupt-router/intel-irq.h>
14 /include/ "skeleton.dtsi"
15 /include/ "serial.dtsi"
17 /include/ "tsc_timer.dtsi"
20 model = "congatec-QEVAL20-QA3-E3845";
21 compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail";
33 compatible = "intel,x86-pinctrl";
37 * As of today, the latest version FSP (gold4) for BayTrail
38 * misses the PAD configuration of the SD controller's Card
39 * Detect signal. The default PAD value for the CD pin sets
40 * the pin to work in GPIO mode, which causes card detect
41 * status cannot be reflected by the Present State register
42 * in the SD controller (bit 16 & bit 18 are always zero).
44 * Configure this pin to function 1 (SD controller).
51 /* Add SMBus PAD configuration */
64 stdout-path = "/serial";
73 compatible = "intel,baytrail-cpu";
80 compatible = "intel,baytrail-cpu";
87 compatible = "intel,baytrail-cpu";
94 compatible = "intel,baytrail-cpu";
101 compatible = "intel,pci-baytrail", "pci-x86";
102 #address-cells = <3>;
105 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
106 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
107 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
110 reg = <0x0000f800 0 0 0 0>;
111 compatible = "pci8086,0f1c", "intel,pch9";
112 #address-cells = <1>;
116 compatible = "intel,irq-router";
117 intel,pirq-config = "ibase";
118 intel,ibase-offset = <0x50>;
119 intel,actl-addr = <0>;
120 intel,pirq-link = <8 8>;
121 intel,pirq-mask = <0xdee0>;
122 intel,pirq-routing = <
123 /* BayTrail PCI devices */
124 PCI_BDF(0, 2, 0) INTA PIRQA
125 PCI_BDF(0, 3, 0) INTA PIRQA
126 PCI_BDF(0, 16, 0) INTA PIRQA
127 PCI_BDF(0, 17, 0) INTA PIRQA
128 PCI_BDF(0, 18, 0) INTA PIRQA
129 PCI_BDF(0, 19, 0) INTA PIRQA
130 PCI_BDF(0, 20, 0) INTA PIRQA
131 PCI_BDF(0, 21, 0) INTA PIRQA
132 PCI_BDF(0, 22, 0) INTA PIRQA
133 PCI_BDF(0, 23, 0) INTA PIRQA
134 PCI_BDF(0, 24, 0) INTA PIRQA
135 PCI_BDF(0, 24, 1) INTC PIRQC
136 PCI_BDF(0, 24, 2) INTD PIRQD
137 PCI_BDF(0, 24, 3) INTB PIRQB
138 PCI_BDF(0, 24, 4) INTA PIRQA
139 PCI_BDF(0, 24, 5) INTC PIRQC
140 PCI_BDF(0, 24, 6) INTD PIRQD
141 PCI_BDF(0, 24, 7) INTB PIRQB
142 PCI_BDF(0, 26, 0) INTA PIRQA
143 PCI_BDF(0, 27, 0) INTA PIRQA
144 PCI_BDF(0, 28, 0) INTA PIRQA
145 PCI_BDF(0, 28, 1) INTB PIRQB
146 PCI_BDF(0, 28, 2) INTC PIRQC
147 PCI_BDF(0, 28, 3) INTD PIRQD
148 PCI_BDF(0, 29, 0) INTA PIRQA
149 PCI_BDF(0, 30, 0) INTA PIRQA
150 PCI_BDF(0, 30, 1) INTD PIRQD
151 PCI_BDF(0, 30, 2) INTB PIRQB
152 PCI_BDF(0, 30, 3) INTC PIRQC
153 PCI_BDF(0, 30, 4) INTD PIRQD
154 PCI_BDF(0, 30, 5) INTB PIRQB
155 PCI_BDF(0, 31, 3) INTB PIRQB
158 * PCIe root ports downstream
161 PCI_BDF(1, 0, 0) INTA PIRQA
162 PCI_BDF(1, 0, 0) INTB PIRQB
163 PCI_BDF(1, 0, 0) INTC PIRQC
164 PCI_BDF(1, 0, 0) INTD PIRQD
165 PCI_BDF(2, 0, 0) INTA PIRQB
166 PCI_BDF(2, 0, 0) INTB PIRQC
167 PCI_BDF(2, 0, 0) INTC PIRQD
168 PCI_BDF(2, 0, 0) INTD PIRQA
169 PCI_BDF(3, 0, 0) INTA PIRQC
170 PCI_BDF(3, 0, 0) INTB PIRQD
171 PCI_BDF(3, 0, 0) INTC PIRQA
172 PCI_BDF(3, 0, 0) INTD PIRQB
173 PCI_BDF(4, 0, 0) INTA PIRQD
174 PCI_BDF(4, 0, 0) INTB PIRQA
175 PCI_BDF(4, 0, 0) INTC PIRQB
176 PCI_BDF(4, 0, 0) INTD PIRQC
181 #address-cells = <1>;
183 compatible = "intel,ich9-spi";
185 #address-cells = <1>;
188 compatible = "stmicro,n25q064a",
190 memory-map = <0xff800000 0x00800000>;
192 label = "rw-mrc-cache";
193 reg = <0x006f0000 0x00010000>;
199 compatible = "intel,ich6-gpio";
207 compatible = "intel,ich6-gpio";
215 compatible = "intel,ich6-gpio";
223 compatible = "intel,ich6-gpio";
231 compatible = "intel,ich6-gpio";
239 compatible = "intel,ich6-gpio";
249 compatible = "intel,baytrail-fsp";
250 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
251 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
252 fsp,mrc-init-spd-addr1 = <0xa0>;
253 fsp,mrc-init-spd-addr2 = <0xa2>;
254 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
260 fsp,sata-mode = <SATA_MODE_AHCI>;
262 fsp,lpss-sio-enable-pci-mode;
267 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
268 fsp,aperture-size = <APERTURE_SIZE_256MB>;
269 fsp,gtt-size = <GTT_SIZE_2MB>;
270 fsp,scc-enable-pci-mode;
271 fsp,os-selection = <OS_SELECTION_LINUX>;
272 fsp,emmc45-ddr50-enabled;
273 fsp,emmc45-retune-timer-value = <8>;
275 fsp,enable-memory-down;
276 fsp,memory-down-params {
277 compatible = "intel,baytrail-fsp-mdp";
278 fsp,dram-speed = <DRAM_SPEED_1333MTS>;
279 fsp,dram-type = <DRAM_TYPE_DDR3L>;
282 fsp,dimm-width = <DIMM_WIDTH_X16>;
283 fsp,dimm-density = <DIMM_DENSITY_4GBIT>;
284 fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>;
285 fsp,dimm-sides = <DIMM_SIDES_1RANKS>;
287 /* These following values might need a re-visit */
289 fsp,dimm-trpt-rcd = <8>;
294 fsp,dimm-tfaw = <22>;
300 #include "microcode/m0130673325.dtsi"
303 #include "microcode/m0130679907.dtsi"