git.sur5r.net Git - u-boot/blob - arch/x86/dts/cougarcanyon2.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
   4  */
   5
   6 /dts-v1/;
   7
   8 /include/ "skeleton.dtsi"
   9 /include/ "serial.dtsi"
  10 /include/ "keyboard.dtsi"
  11 /include/ "rtc.dtsi"
  12 /include/ "tsc_timer.dtsi"
  13
  14 / {
  15         model = "Intel Cougar Canyon 2";
  16         compatible = "intel,cougarcanyon2", "intel,chiefriver";
  17
  18         aliases {
  19                 spi0 = &spi0;
  20         };
  21
  22         config {
  23                 silent_console = <0>;
  24         };
  25
  26         chosen {
  27                 stdout-path = "/serial";
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "intel,core-gen3";
  37                         reg = <0>;
  38                         intel,apic-id = <0>;
  39                 };
  40
  41                 cpu@1 {
  42                         device_type = "cpu";
  43                         compatible = "intel,core-gen3";
  44                         reg = <1>;
  45                         intel,apic-id = <1>;
  46                 };
  47
  48                 cpu@2 {
  49                         device_type = "cpu";
  50                         compatible = "intel,core-gen3";
  51                         reg = <2>;
  52                         intel,apic-id = <2>;
  53                 };
  54
  55                 cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "intel,core-gen3";
  58                         reg = <3>;
  59                         intel,apic-id = <3>;
  60                 };
  61         };
  62
  63         microcode {
  64                 update@0 {
  65 #include "microcode/m12306a2_00000008.dtsi"
  66                 };
  67                 update@1 {
  68 #include "microcode/m12306a4_00000007.dtsi"
  69                 };
  70                 update@2 {
  71 #include "microcode/m12306a5_00000007.dtsi"
  72                 };
  73                 update@3 {
  74 #include "microcode/m12306a8_00000010.dtsi"
  75                 };
  76                 update@4 {
  77 #include "microcode/m12306a9_0000001b.dtsi"
  78                 };
  79         };
  80
  81         fsp {
  82                 compatible = "intel,ivybridge-fsp";
  83                 fsp,enable-ht;
  84         };
  85
  86         pci {
  87                 #address-cells = <3>;
  88                 #size-cells = <2>;
  89                 compatible = "pci-x86";
  90                 u-boot,dm-pre-reloc;
  91                 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
  92                           0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
  93                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  94
  95                 pch@1f,0 {
  96                         reg = <0x0000f800 0 0 0 0>;
  97                         compatible = "intel,bd82x6x";
  98                         u-boot,dm-pre-reloc;
  99                         #address-cells = <1>;
 100                         #size-cells = <1>;
 101
 102                         spi0: spi {
 103                                 #address-cells = <1>;
 104                                 #size-cells = <0>;
 105                                 compatible = "intel,ich9-spi";
 106                                 intel,spi-lock-down;
 107
 108                                 spi-flash@0 {
 109                                         reg = <0>;
 110                                         compatible = "winbond,w25q64bv", "spi-flash";
 111                                         memory-map = <0xff800000 0x00800000>;
 112                                 };
 113                         };
 114
 115                         gpioa {
 116                                 compatible = "intel,ich6-gpio";
 117                                 u-boot,dm-pre-reloc;
 118                                 reg = <0 0x10>;
 119                                 bank-name = "A";
 120                         };
 121
 122                         gpiob {
 123                                 compatible = "intel,ich6-gpio";
 124                                 u-boot,dm-pre-reloc;
 125                                 reg = <0x30 0x10>;
 126                                 bank-name = "B";
 127                         };
 128
 129                         gpioc {
 130                                 compatible = "intel,ich6-gpio";
 131                                 u-boot,dm-pre-reloc;
 132                                 reg = <0x40 0x10>;
 133                                 bank-name = "C";
 134                         };
 135                 };
 136         };
 137
 138 };