git.sur5r.net Git - u-boot/blob - arch/x86/dts/cougarcanyon2.dts

   1 /*
   2  * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /dts-v1/;
   8
   9 /include/ "skeleton.dtsi"
  10 /include/ "serial.dtsi"
  11 /include/ "keyboard.dtsi"
  12 /include/ "rtc.dtsi"
  13 /include/ "tsc_timer.dtsi"
  14
  15 / {
  16         model = "Intel Cougar Canyon 2";
  17         compatible = "intel,cougarcanyon2", "intel,chiefriver";
  18
  19         aliases {
  20                 spi0 = &spi0;
  21         };
  22
  23         config {
  24                 silent_console = <0>;
  25         };
  26
  27         chosen {
  28                 stdout-path = "/serial";
  29         };
  30
  31         microcode {
  32                 update@0 {
  33 #include "microcode/m12306a2_00000008.dtsi"
  34                 };
  35                 update@1 {
  36 #include "microcode/m12306a4_00000007.dtsi"
  37                 };
  38                 update@2 {
  39 #include "microcode/m12306a5_00000007.dtsi"
  40                 };
  41                 update@3 {
  42 #include "microcode/m12306a8_00000010.dtsi"
  43                 };
  44                 update@4 {
  45 #include "microcode/m12306a9_0000001b.dtsi"
  46                 };
  47         };
  48
  49         fsp {
  50                 compatible = "intel,ivybridge-fsp";
  51                 fsp,enable-ht;
  52         };
  53
  54         pci {
  55                 #address-cells = <3>;
  56                 #size-cells = <2>;
  57                 compatible = "pci-x86";
  58                 u-boot,dm-pre-reloc;
  59                 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
  60                           0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
  61                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  62
  63                 pch@1f,0 {
  64                         reg = <0x0000f800 0 0 0 0>;
  65                         compatible = "intel,bd82x6x";
  66                         u-boot,dm-pre-reloc;
  67                         #address-cells = <1>;
  68                         #size-cells = <1>;
  69
  70                         spi0: spi {
  71                                 #address-cells = <1>;
  72                                 #size-cells = <0>;
  73                                 compatible = "intel,ich9-spi";
  74                                 spi-flash@0 {
  75                                         reg = <0>;
  76                                         compatible = "winbond,w25q64bv", "spi-flash";
  77                                         memory-map = <0xff800000 0x00800000>;
  78                                 };
  79                         };
  80
  81                         gpioa {
  82                                 compatible = "intel,ich6-gpio";
  83                                 u-boot,dm-pre-reloc;
  84                                 reg = <0 0x10>;
  85                                 bank-name = "A";
  86                         };
  87
  88                         gpiob {
  89                                 compatible = "intel,ich6-gpio";
  90                                 u-boot,dm-pre-reloc;
  91                                 reg = <0x30 0x10>;
  92                                 bank-name = "B";
  93                         };
  94
  95                         gpioc {
  96                                 compatible = "intel,ich6-gpio";
  97                                 u-boot,dm-pre-reloc;
  98                                 reg = <0x40 0x10>;
  99                                 bank-name = "C";
 100                         };
 101                 };
 102         };
 103
 104 };