3 /include/ "coreboot.dtsi"
9 compatible = "google,link", "intel,celeron-ivybridge";
16 compatible = "intel,ich6-gpio";
22 compatible = "intel,ich6-gpio";
28 compatible = "intel,ich6-gpio";
35 clock-frequency = <115200>;
39 memory { device_type = "memory"; reg = <0 0>; };
44 compatible = "intel,ich9";
47 compatible = "winbond,w25q64", "spi-flash";
48 memory-map = <0xff800000 0x00800000>;
53 compatible = "intel,lpc";
56 gen-dec = <0x800 0xfc 0x900 0xfc>;
58 compatible = "google,cros-ec";
59 reg = <0x204 1 0x200 1 0x880 0x80>;
61 /* This describes the flash memory within the EC */
65 reg = <0x08000000 0x20000>;