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x86: Add support for the samus chromebook
[u-boot] / arch / x86 / dts / minnowmax.dts
1 /*
2  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /dts-v1/;
8
9 #include <dt-bindings/gpio/x86-gpio.h>
10 #include <dt-bindings/interrupt-router/intel-irq.h>
11
12 /include/ "skeleton.dtsi"
13 /include/ "serial.dtsi"
14 /include/ "rtc.dtsi"
15 /include/ "tsc_timer.dtsi"
16
17 / {
18         model = "Intel Minnowboard Max";
19         compatible = "intel,minnowmax", "intel,baytrail";
20
21         aliases {
22                 serial0 = &serial;
23                 spi0 = &spi;
24         };
25
26         config {
27                 silent_console = <0>;
28         };
29
30         pch_pinctrl {
31                 compatible = "intel,x86-pinctrl";
32
33                 /* GPIO E0 */
34                 soc_gpio_s5_0@0 {
35                         gpio-offset = <0x80 0>;
36                         pad-offset = <0x1d0>;
37                         mode-gpio;
38                         output-value = <0>;
39                         direction = <PIN_OUTPUT>;
40                 };
41
42                 /* GPIO E1 */
43                 soc_gpio_s5_1@0 {
44                         gpio-offset = <0x80 1>;
45                         pad-offset = <0x210>;
46                         mode-gpio;
47                         output-value = <0>;
48                         direction = <PIN_OUTPUT>;
49                 };
50
51                 /* GPIO E2 */
52                 soc_gpio_s5_2@0 {
53                         gpio-offset = <0x80 2>;
54                         pad-offset = <0x1e0>;
55                         mode-gpio;
56                         output-value = <0>;
57                         direction = <PIN_OUTPUT>;
58                 };
59
60                 pin_usb_host_en0@0 {
61                         gpio-offset = <0x80 8>;
62                         pad-offset = <0x260>;
63                         mode-gpio;
64                         output-value = <1>;
65                         direction = <PIN_OUTPUT>;
66                 };
67
68                 pin_usb_host_en1@0 {
69                         gpio-offset = <0x80 9>;
70                         pad-offset = <0x250>;
71                         mode-gpio;
72                         output-value = <1>;
73                         direction = <PIN_OUTPUT>;
74                 };
75         };
76
77         chosen {
78                 stdout-path = "/serial";
79         };
80
81         cpus {
82                 #address-cells = <1>;
83                 #size-cells = <0>;
84
85                 cpu@0 {
86                         device_type = "cpu";
87                         compatible = "intel,baytrail-cpu";
88                         reg = <0>;
89                         intel,apic-id = <0>;
90                 };
91
92                 cpu@1 {
93                         device_type = "cpu";
94                         compatible = "intel,baytrail-cpu";
95                         reg = <1>;
96                         intel,apic-id = <4>;
97                 };
98
99         };
100
101         pci {
102                 compatible = "intel,pci-baytrail", "pci-x86";
103                 #address-cells = <3>;
104                 #size-cells = <2>;
105                 u-boot,dm-pre-reloc;
106                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
107                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
108                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
109
110                 pch@1f,0 {
111                         reg = <0x0000f800 0 0 0 0>;
112                         compatible = "pci8086,0f1c", "intel,pch9";
113                         #address-cells = <1>;
114                         #size-cells = <1>;
115
116                         irq-router {
117                                 compatible = "intel,irq-router";
118                                 intel,pirq-config = "ibase";
119                                 intel,ibase-offset = <0x50>;
120                                 intel,pirq-link = <8 8>;
121                                 intel,pirq-mask = <0xdee0>;
122                                 intel,pirq-routing = <
123                                         /* BayTrail PCI devices */
124                                         PCI_BDF(0, 2, 0) INTA PIRQA
125                                         PCI_BDF(0, 3, 0) INTA PIRQA
126                                         PCI_BDF(0, 16, 0) INTA PIRQA
127                                         PCI_BDF(0, 17, 0) INTA PIRQA
128                                         PCI_BDF(0, 18, 0) INTA PIRQA
129                                         PCI_BDF(0, 19, 0) INTA PIRQA
130                                         PCI_BDF(0, 20, 0) INTA PIRQA
131                                         PCI_BDF(0, 21, 0) INTA PIRQA
132                                         PCI_BDF(0, 22, 0) INTA PIRQA
133                                         PCI_BDF(0, 23, 0) INTA PIRQA
134                                         PCI_BDF(0, 24, 0) INTA PIRQA
135                                         PCI_BDF(0, 24, 1) INTC PIRQC
136                                         PCI_BDF(0, 24, 2) INTD PIRQD
137                                         PCI_BDF(0, 24, 3) INTB PIRQB
138                                         PCI_BDF(0, 24, 4) INTA PIRQA
139                                         PCI_BDF(0, 24, 5) INTC PIRQC
140                                         PCI_BDF(0, 24, 6) INTD PIRQD
141                                         PCI_BDF(0, 24, 7) INTB PIRQB
142                                         PCI_BDF(0, 26, 0) INTA PIRQA
143                                         PCI_BDF(0, 27, 0) INTA PIRQA
144                                         PCI_BDF(0, 28, 0) INTA PIRQA
145                                         PCI_BDF(0, 28, 1) INTB PIRQB
146                                         PCI_BDF(0, 28, 2) INTC PIRQC
147                                         PCI_BDF(0, 28, 3) INTD PIRQD
148                                         PCI_BDF(0, 29, 0) INTA PIRQA
149                                         PCI_BDF(0, 30, 0) INTA PIRQA
150                                         PCI_BDF(0, 30, 1) INTD PIRQD
151                                         PCI_BDF(0, 30, 2) INTB PIRQB
152                                         PCI_BDF(0, 30, 3) INTC PIRQC
153                                         PCI_BDF(0, 30, 4) INTD PIRQD
154                                         PCI_BDF(0, 30, 5) INTB PIRQB
155                                         PCI_BDF(0, 31, 3) INTB PIRQB
156
157                                         /*
158                                          * PCIe root ports downstream
159                                          * interrupts
160                                          */
161                                         PCI_BDF(1, 0, 0) INTA PIRQA
162                                         PCI_BDF(1, 0, 0) INTB PIRQB
163                                         PCI_BDF(1, 0, 0) INTC PIRQC
164                                         PCI_BDF(1, 0, 0) INTD PIRQD
165                                         PCI_BDF(2, 0, 0) INTA PIRQB
166                                         PCI_BDF(2, 0, 0) INTB PIRQC
167                                         PCI_BDF(2, 0, 0) INTC PIRQD
168                                         PCI_BDF(2, 0, 0) INTD PIRQA
169                                         PCI_BDF(3, 0, 0) INTA PIRQC
170                                         PCI_BDF(3, 0, 0) INTB PIRQD
171                                         PCI_BDF(3, 0, 0) INTC PIRQA
172                                         PCI_BDF(3, 0, 0) INTD PIRQB
173                                         PCI_BDF(4, 0, 0) INTA PIRQD
174                                         PCI_BDF(4, 0, 0) INTB PIRQA
175                                         PCI_BDF(4, 0, 0) INTC PIRQB
176                                         PCI_BDF(4, 0, 0) INTD PIRQC
177                                 >;
178                         };
179
180                         spi: spi {
181                                 #address-cells = <1>;
182                                 #size-cells = <0>;
183                                 compatible = "intel,ich9-spi";
184                                 spi-flash@0 {
185                                         #address-cells = <1>;
186                                         #size-cells = <1>;
187                                         reg = <0>;
188                                         compatible = "stmicro,n25q064a",
189                                                 "spi-flash";
190                                         memory-map = <0xff800000 0x00800000>;
191                                         rw-mrc-cache {
192                                                 label = "rw-mrc-cache";
193                                                 reg = <0x006f0000 0x00010000>;
194                                         };
195                                 };
196                         };
197
198                         gpioa {
199                                 compatible = "intel,ich6-gpio";
200                                 u-boot,dm-pre-reloc;
201                                 reg = <0 0x20>;
202                                 bank-name = "A";
203                         };
204
205                         gpiob {
206                                 compatible = "intel,ich6-gpio";
207                                 u-boot,dm-pre-reloc;
208                                 reg = <0x20 0x20>;
209                                 bank-name = "B";
210                         };
211
212                         gpioc {
213                                 compatible = "intel,ich6-gpio";
214                                 u-boot,dm-pre-reloc;
215                                 reg = <0x40 0x20>;
216                                 bank-name = "C";
217                         };
218
219                         gpiod {
220                                 compatible = "intel,ich6-gpio";
221                                 u-boot,dm-pre-reloc;
222                                 reg = <0x60 0x20>;
223                                 bank-name = "D";
224                         };
225
226                         gpioe {
227                                 compatible = "intel,ich6-gpio";
228                                 u-boot,dm-pre-reloc;
229                                 reg = <0x80 0x20>;
230                                 bank-name = "E";
231                         };
232
233                         gpiof {
234                                 compatible = "intel,ich6-gpio";
235                                 u-boot,dm-pre-reloc;
236                                 reg = <0xA0 0x20>;
237                                 bank-name = "F";
238                         };
239                 };
240         };
241
242         fsp {
243                 compatible = "intel,baytrail-fsp";
244                 fsp,mrc-init-tseg-size = <0>;
245                 fsp,mrc-init-mmio-size = <0x800>;
246                 fsp,mrc-init-spd-addr1 = <0xa0>;
247                 fsp,mrc-init-spd-addr2 = <0xa2>;
248                 fsp,emmc-boot-mode = <2>;
249                 fsp,enable-sdio;
250                 fsp,enable-sdcard;
251                 fsp,enable-hsuart1;
252                 fsp,enable-spi;
253                 fsp,enable-sata;
254                 fsp,sata-mode = <1>;
255                 fsp,enable-lpe;
256                 fsp,lpss-sio-enable-pci-mode;
257                 fsp,enable-dma0;
258                 fsp,enable-dma1;
259                 fsp,enable-i2c0;
260                 fsp,enable-i2c1;
261                 fsp,enable-i2c2;
262                 fsp,enable-i2c3;
263                 fsp,enable-i2c4;
264                 fsp,enable-i2c5;
265                 fsp,enable-i2c6;
266                 fsp,enable-pwm0;
267                 fsp,enable-pwm1;
268                 fsp,igd-dvmt50-pre-alloc = <2>;
269                 fsp,aperture-size = <2>;
270                 fsp,gtt-size = <2>;
271                 fsp,serial-debug-port-address = <0x3f8>;
272                 fsp,serial-debug-port-type = <1>;
273                 fsp,scc-enable-pci-mode;
274                 fsp,os-selection = <4>;
275                 fsp,emmc45-ddr50-enabled;
276                 fsp,emmc45-retune-timer-value = <8>;
277                 fsp,enable-igd;
278                 fsp,enable-memory-down;
279                 fsp,memory-down-params {
280                         compatible = "intel,baytrail-fsp-mdp";
281                         fsp,dram-speed = <1>;
282                         fsp,dram-type = <1>;
283                         fsp,dimm-0-enable;
284                         fsp,dimm-width = <1>;
285                         fsp,dimm-density = <2>;
286                         fsp,dimm-bus-width = <3>;
287                         fsp,dimm-sides = <0>;
288                         fsp,dimm-tcl = <0xb>;
289                         fsp,dimm-trpt-rcd = <0xb>;
290                         fsp,dimm-twr = <0xc>;
291                         fsp,dimm-twtr = <6>;
292                         fsp,dimm-trrd = <6>;
293                         fsp,dimm-trtp = <6>;
294                         fsp,dimm-tfaw = <0x14>;
295                 };
296         };
297
298         microcode {
299                 update@0 {
300 #include "microcode/m0130673322.dtsi"
301                 };
302                 update@1 {
303 #include "microcode/m0130679901.dtsi"
304                 };
305         };
306
307 };