2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <dt-bindings/gpio/x86-gpio.h>
10 #include <dt-bindings/interrupt-router/intel-irq.h>
12 /include/ "skeleton.dtsi"
13 /include/ "serial.dtsi"
15 /include/ "tsc_timer.dtsi"
16 /include/ "coreboot_fb.dtsi"
19 model = "Intel Minnowboard Max";
20 compatible = "intel,minnowmax", "intel,baytrail";
32 compatible = "intel,x86-pinctrl";
37 gpio-offset = <0x80 0>;
41 direction = <PIN_OUTPUT>;
46 gpio-offset = <0x80 1>;
50 direction = <PIN_OUTPUT>;
55 gpio-offset = <0x80 2>;
59 direction = <PIN_OUTPUT>;
63 gpio-offset = <0x80 8>;
67 direction = <PIN_OUTPUT>;
71 gpio-offset = <0x80 9>;
75 direction = <PIN_OUTPUT>;
79 * As of today, the latest version FSP (gold4) for BayTrail
80 * misses the PAD configuration of the SD controller's Card
81 * Detect signal. The default PAD value for the CD pin sets
82 * the pin to work in GPIO mode, which causes card detect
83 * status cannot be reflected by the Present State register
84 * in the SD controller (bit 16 & bit 18 are always zero).
86 * Configure this pin to function 1 (SD controller).
95 stdout-path = "/serial";
104 compatible = "intel,baytrail-cpu";
111 compatible = "intel,baytrail-cpu";
119 compatible = "intel,pci-baytrail", "pci-x86";
120 #address-cells = <3>;
123 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
124 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
125 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
128 reg = <0x0000f800 0 0 0 0>;
129 compatible = "pci8086,0f1c", "intel,pch9";
130 #address-cells = <1>;
134 compatible = "intel,irq-router";
135 intel,pirq-config = "ibase";
136 intel,ibase-offset = <0x50>;
137 intel,actl-addr = <0>;
138 intel,pirq-link = <8 8>;
139 intel,pirq-mask = <0xdee0>;
140 intel,pirq-routing = <
141 /* BayTrail PCI devices */
142 PCI_BDF(0, 2, 0) INTA PIRQA
143 PCI_BDF(0, 3, 0) INTA PIRQA
144 PCI_BDF(0, 16, 0) INTA PIRQA
145 PCI_BDF(0, 17, 0) INTA PIRQA
146 PCI_BDF(0, 18, 0) INTA PIRQA
147 PCI_BDF(0, 19, 0) INTA PIRQA
148 PCI_BDF(0, 20, 0) INTA PIRQA
149 PCI_BDF(0, 21, 0) INTA PIRQA
150 PCI_BDF(0, 22, 0) INTA PIRQA
151 PCI_BDF(0, 23, 0) INTA PIRQA
152 PCI_BDF(0, 24, 0) INTA PIRQA
153 PCI_BDF(0, 24, 1) INTC PIRQC
154 PCI_BDF(0, 24, 2) INTD PIRQD
155 PCI_BDF(0, 24, 3) INTB PIRQB
156 PCI_BDF(0, 24, 4) INTA PIRQA
157 PCI_BDF(0, 24, 5) INTC PIRQC
158 PCI_BDF(0, 24, 6) INTD PIRQD
159 PCI_BDF(0, 24, 7) INTB PIRQB
160 PCI_BDF(0, 26, 0) INTA PIRQA
161 PCI_BDF(0, 27, 0) INTA PIRQA
162 PCI_BDF(0, 28, 0) INTA PIRQA
163 PCI_BDF(0, 28, 1) INTB PIRQB
164 PCI_BDF(0, 28, 2) INTC PIRQC
165 PCI_BDF(0, 28, 3) INTD PIRQD
166 PCI_BDF(0, 29, 0) INTA PIRQA
167 PCI_BDF(0, 30, 0) INTA PIRQA
168 PCI_BDF(0, 30, 1) INTD PIRQD
169 PCI_BDF(0, 30, 2) INTB PIRQB
170 PCI_BDF(0, 30, 3) INTC PIRQC
171 PCI_BDF(0, 30, 4) INTD PIRQD
172 PCI_BDF(0, 30, 5) INTB PIRQB
173 PCI_BDF(0, 31, 3) INTB PIRQB
176 * PCIe root ports downstream
179 PCI_BDF(1, 0, 0) INTA PIRQA
180 PCI_BDF(1, 0, 0) INTB PIRQB
181 PCI_BDF(1, 0, 0) INTC PIRQC
182 PCI_BDF(1, 0, 0) INTD PIRQD
183 PCI_BDF(2, 0, 0) INTA PIRQB
184 PCI_BDF(2, 0, 0) INTB PIRQC
185 PCI_BDF(2, 0, 0) INTC PIRQD
186 PCI_BDF(2, 0, 0) INTD PIRQA
187 PCI_BDF(3, 0, 0) INTA PIRQC
188 PCI_BDF(3, 0, 0) INTB PIRQD
189 PCI_BDF(3, 0, 0) INTC PIRQA
190 PCI_BDF(3, 0, 0) INTD PIRQB
191 PCI_BDF(4, 0, 0) INTA PIRQD
192 PCI_BDF(4, 0, 0) INTB PIRQA
193 PCI_BDF(4, 0, 0) INTC PIRQB
194 PCI_BDF(4, 0, 0) INTD PIRQC
199 #address-cells = <1>;
201 compatible = "intel,ich9-spi";
203 #address-cells = <1>;
206 compatible = "stmicro,n25q064a",
208 memory-map = <0xff800000 0x00800000>;
210 label = "rw-mrc-cache";
211 reg = <0x006f0000 0x00010000>;
217 compatible = "intel,ich6-gpio";
224 compatible = "intel,ich6-gpio";
231 compatible = "intel,ich6-gpio";
238 compatible = "intel,ich6-gpio";
245 compatible = "intel,ich6-gpio";
252 compatible = "intel,ich6-gpio";
261 compatible = "intel,baytrail-fsp";
262 fsp,mrc-init-tseg-size = <0>;
263 fsp,mrc-init-mmio-size = <0x800>;
264 fsp,mrc-init-spd-addr1 = <0xa0>;
265 fsp,mrc-init-spd-addr2 = <0xa2>;
266 fsp,emmc-boot-mode = <1>;
274 fsp,lpss-sio-enable-pci-mode;
286 fsp,igd-dvmt50-pre-alloc = <2>;
287 fsp,aperture-size = <2>;
289 fsp,serial-debug-port-address = <0x3f8>;
290 fsp,serial-debug-port-type = <1>;
291 fsp,scc-enable-pci-mode;
292 fsp,os-selection = <4>;
293 fsp,emmc45-ddr50-enabled;
294 fsp,emmc45-retune-timer-value = <8>;
296 fsp,enable-memory-down;
297 fsp,memory-down-params {
298 compatible = "intel,baytrail-fsp-mdp";
299 fsp,dram-speed = <1>;
302 fsp,dimm-width = <1>;
303 fsp,dimm-density = <2>;
304 fsp,dimm-bus-width = <3>;
305 fsp,dimm-sides = <0>;
306 fsp,dimm-tcl = <0xb>;
307 fsp,dimm-trpt-rcd = <0xb>;
308 fsp,dimm-twr = <0xc>;
312 fsp,dimm-tfaw = <0x14>;
318 #include "microcode/m0130673325.dtsi"
321 #include "microcode/m0130679907.dtsi"