git.sur5r.net Git - u-boot/blob - arch/x86/dts/u-boot.dtsi

   1 /*
   2  * Copyright (C) 2016 Google, Inc
   3  * Written by Simon Glass <sjg@chromium.org>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <config.h>
   9
  10 #ifdef CONFIG_ROM_SIZE
  11 / {
  12         binman {
  13                 filename = "u-boot.rom";
  14                 end-at-4gb;
  15                 sort-by-pos;
  16                 pad-byte = <0xff>;
  17                 size = <CONFIG_ROM_SIZE>;
  18 #ifdef CONFIG_HAVE_INTEL_ME
  19                 intel-descriptor {
  20                 };
  21                 intel-me {
  22                 };
  23 #endif
  24 #ifdef CONFIG_SPL
  25                 u-boot-spl-with-ucode-ptr {
  26                         pos = <CONFIG_SPL_TEXT_BASE>;
  27                 };
  28
  29                 u-boot-dtb-with-ucode2 {
  30                         type = "u-boot-dtb-with-ucode";
  31                 };
  32                 u-boot {
  33                         pos = <0xfff00000>;
  34                 };
  35 #else
  36                 u-boot-with-ucode-ptr {
  37                         pos = <CONFIG_SYS_TEXT_BASE>;
  38                 };
  39 #endif
  40                 u-boot-dtb-with-ucode {
  41                 };
  42                 u-boot-ucode {
  43                         align = <16>;
  44                 };
  45 #ifdef CONFIG_HAVE_MRC
  46                 intel-mrc {
  47                         pos = <CONFIG_X86_MRC_ADDR>;
  48                 };
  49 #endif
  50 #ifdef CONFIG_HAVE_FSP
  51                 intel-fsp {
  52                         filename = CONFIG_FSP_FILE;
  53                         pos = <CONFIG_FSP_ADDR>;
  54                 };
  55 #endif
  56 #ifdef CONFIG_HAVE_CMC
  57                 intel-cmc {
  58                         filename = CONFIG_CMC_FILE;
  59                         pos = <CONFIG_CMC_ADDR>;
  60                 };
  61 #endif
  62 #ifdef CONFIG_HAVE_VGA_BIOS
  63                 intel-vga {
  64                         filename = CONFIG_VGA_BIOS_FILE;
  65                         pos = <CONFIG_VGA_BIOS_ADDR>;
  66                 };
  67 #endif
  68 #ifdef CONFIG_HAVE_REFCODE
  69                 intel-refcode {
  70                         pos = <CONFIG_X86_REFCODE_ADDR>;
  71                 };
  72 #endif
  73 #ifdef CONFIG_SPL
  74                 x86-start16-spl {
  75                         pos = <CONFIG_SYS_X86_START16>;
  76                 };
  77 #else
  78                 x86-start16 {
  79                         pos = <CONFIG_SYS_X86_START16>;
  80                 };
  81 #endif
  82         };
  83 };
  84 #endif