2 * Copyright (C) 2013 Google Inc.
3 * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
5 * Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef _BAYTRAIL_IOMAP_H_
11 #define _BAYTRAIL_IOMAP_H_
13 /* Memory Mapped IO bases */
15 /* PCI Configuration Space */
16 #define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE
17 #define MCFG_BASE_SIZE 0x10000000
19 /* Temporary Base Address */
20 #define TEMP_BASE_ADDRESS 0xfd000000
22 /* Transactions in this range will abort */
23 #define ABORT_BASE_ADDRESS 0xfeb00000
24 #define ABORT_BASE_SIZE 0x00100000
26 /* High Performance Event Timer */
27 #define HPET_BASE_ADDRESS 0xfed00000
28 #define HPET_BASE_SIZE 0x400
31 #define SPI_BASE_ADDRESS 0xfed01000
32 #define SPI_BASE_SIZE 0x400
34 /* Power Management Controller */
35 #define PMC_BASE_ADDRESS 0xfed03000
36 #define PMC_BASE_SIZE 0x400
38 /* Power Management Unit */
39 #define PUNIT_BASE_ADDRESS 0xfed05000
40 #define PUNIT_BASE_SIZE 0x800
42 /* Intel Legacy Block */
43 #define ILB_BASE_ADDRESS 0xfed08000
44 #define ILB_BASE_SIZE 0x400
47 #define IO_BASE_ADDRESS 0xfed0c000
48 #define IO_BASE_OFFSET_GPSCORE 0x0000
49 #define IO_BASE_OFFSET_GPNCORE 0x1000
50 #define IO_BASE_OFFSET_GPSSUS 0x2000
51 #define IO_BASE_SIZE 0x4000
53 /* Root Complex Base Address */
54 #define RCBA_BASE_ADDRESS 0xfed1c000
55 #define RCBA_BASE_SIZE 0x400
58 #define MPHY_BASE_ADDRESS 0xfef00000
59 #define MPHY_BASE_SIZE 0x100000
62 #define ACPI_BASE_ADDRESS 0x0400
63 #define ACPI_BASE_SIZE 0x80
65 #define GPIO_BASE_ADDRESS 0x0500
66 #define GPIO_BASE_SIZE 0x100
68 #define SMBUS_BASE_ADDRESS 0xefa0
70 #endif /* _BAYTRAIL_IOMAP_H_ */