git.sur5r.net Git - u-boot/blob - arch/x86/include/asm/arch-baytrail/irq.h

   1 /*
   2  * Copyright (C) 2013 Google Inc.
   3  * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
   4  *
   5  * Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _BAYTRAIL_IRQ_H_
  11 #define _BAYTRAIL_IRQ_H_
  12
  13 #define PIRQA_APIC_IRQ                  16
  14 #define PIRQB_APIC_IRQ                  17
  15 #define PIRQC_APIC_IRQ                  18
  16 #define PIRQD_APIC_IRQ                  19
  17 #define PIRQE_APIC_IRQ                  20
  18 #define PIRQF_APIC_IRQ                  21
  19 #define PIRQG_APIC_IRQ                  22
  20 #define PIRQH_APIC_IRQ                  23
  21
  22 /* The below IRQs are for when devices are in ACPI mode */
  23 #define LPE_DMA0_IRQ                    24
  24 #define LPE_DMA1_IRQ                    25
  25 #define LPE_SSP0_IRQ                    26
  26 #define LPE_SSP1_IRQ                    27
  27 #define LPE_SSP2_IRQ                    28
  28 #define LPE_IPC2HOST_IRQ                29
  29 #define LPSS_I2C1_IRQ                   32
  30 #define LPSS_I2C2_IRQ                   33
  31 #define LPSS_I2C3_IRQ                   34
  32 #define LPSS_I2C4_IRQ                   35
  33 #define LPSS_I2C5_IRQ                   36
  34 #define LPSS_I2C6_IRQ                   37
  35 #define LPSS_I2C7_IRQ                   38
  36 #define LPSS_HSUART1_IRQ                39
  37 #define LPSS_HSUART2_IRQ                40
  38 #define LPSS_SPI_IRQ                    41
  39 #define LPSS_DMA1_IRQ                   42
  40 #define LPSS_DMA2_IRQ                   43
  41 #define SCC_EMMC_IRQ                    44
  42 #define SCC_SDIO_IRQ                    46
  43 #define SCC_SD_IRQ                      47
  44 #define GPIO_NC_IRQ                     48
  45 #define GPIO_SC_IRQ                     49
  46 #define GPIO_SUS_IRQ                    50
  47 /* GPIO direct / dedicated IRQs */
  48 #define GPIO_S0_DED_IRQ_0               51
  49 #define GPIO_S0_DED_IRQ_1               52
  50 #define GPIO_S0_DED_IRQ_2               53
  51 #define GPIO_S0_DED_IRQ_3               54
  52 #define GPIO_S0_DED_IRQ_4               55
  53 #define GPIO_S0_DED_IRQ_5               56
  54 #define GPIO_S0_DED_IRQ_6               57
  55 #define GPIO_S0_DED_IRQ_7               58
  56 #define GPIO_S0_DED_IRQ_8               59
  57 #define GPIO_S0_DED_IRQ_9               60
  58 #define GPIO_S0_DED_IRQ_10              61
  59 #define GPIO_S0_DED_IRQ_11              62
  60 #define GPIO_S0_DED_IRQ_12              63
  61 #define GPIO_S0_DED_IRQ_13              64
  62 #define GPIO_S0_DED_IRQ_14              65
  63 #define GPIO_S0_DED_IRQ_15              66
  64 #define GPIO_S5_DED_IRQ_0               67
  65 #define GPIO_S5_DED_IRQ_1               68
  66 #define GPIO_S5_DED_IRQ_2               69
  67 #define GPIO_S5_DED_IRQ_3               70
  68 #define GPIO_S5_DED_IRQ_4               71
  69 #define GPIO_S5_DED_IRQ_5               72
  70 #define GPIO_S5_DED_IRQ_6               73
  71 #define GPIO_S5_DED_IRQ_7               74
  72 #define GPIO_S5_DED_IRQ_8               75
  73 #define GPIO_S5_DED_IRQ_9               76
  74 #define GPIO_S5_DED_IRQ_10              77
  75 #define GPIO_S5_DED_IRQ_11              78
  76 #define GPIO_S5_DED_IRQ_12              79
  77 #define GPIO_S5_DED_IRQ_13              80
  78 #define GPIO_S5_DED_IRQ_14              81
  79 #define GPIO_S5_DED_IRQ_15              82
  80 /* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */
  81 #define _GPIO_S0_DED_IRQ(slot)          GPIO_S0_DED_IRQ_##slot
  82 #define _GPIO_S5_DED_IRQ(slot)          GPIO_S5_DED_IRQ_##slot
  83 #define GPIO_S0_DED_IRQ(slot)           _GPIO_S0_DED_IRQ(slot)
  84 #define GPIO_S5_DED_IRQ(slot)           _GPIO_S5_DED_IRQ(slot)
  85
  86 #endif /* _BAYTRAIL_IRQ_H_ */