1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013 Google Inc.
4 * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
6 * Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h
9 #ifndef _BAYTRAIL_IRQ_H_
10 #define _BAYTRAIL_IRQ_H_
12 #define PIRQA_APIC_IRQ 16
13 #define PIRQB_APIC_IRQ 17
14 #define PIRQC_APIC_IRQ 18
15 #define PIRQD_APIC_IRQ 19
16 #define PIRQE_APIC_IRQ 20
17 #define PIRQF_APIC_IRQ 21
18 #define PIRQG_APIC_IRQ 22
19 #define PIRQH_APIC_IRQ 23
21 /* The below IRQs are for when devices are in ACPI mode */
22 #define LPE_DMA0_IRQ 24
23 #define LPE_DMA1_IRQ 25
24 #define LPE_SSP0_IRQ 26
25 #define LPE_SSP1_IRQ 27
26 #define LPE_SSP2_IRQ 28
27 #define LPE_IPC2HOST_IRQ 29
28 #define LPSS_I2C1_IRQ 32
29 #define LPSS_I2C2_IRQ 33
30 #define LPSS_I2C3_IRQ 34
31 #define LPSS_I2C4_IRQ 35
32 #define LPSS_I2C5_IRQ 36
33 #define LPSS_I2C6_IRQ 37
34 #define LPSS_I2C7_IRQ 38
35 #define LPSS_HSUART1_IRQ 39
36 #define LPSS_HSUART2_IRQ 40
37 #define LPSS_SPI_IRQ 41
38 #define LPSS_DMA1_IRQ 42
39 #define LPSS_DMA2_IRQ 43
40 #define SCC_EMMC_IRQ 44
41 #define SCC_SDIO_IRQ 46
43 #define GPIO_NC_IRQ 48
44 #define GPIO_SC_IRQ 49
45 #define GPIO_SUS_IRQ 50
46 /* GPIO direct / dedicated IRQs */
47 #define GPIO_S0_DED_IRQ_0 51
48 #define GPIO_S0_DED_IRQ_1 52
49 #define GPIO_S0_DED_IRQ_2 53
50 #define GPIO_S0_DED_IRQ_3 54
51 #define GPIO_S0_DED_IRQ_4 55
52 #define GPIO_S0_DED_IRQ_5 56
53 #define GPIO_S0_DED_IRQ_6 57
54 #define GPIO_S0_DED_IRQ_7 58
55 #define GPIO_S0_DED_IRQ_8 59
56 #define GPIO_S0_DED_IRQ_9 60
57 #define GPIO_S0_DED_IRQ_10 61
58 #define GPIO_S0_DED_IRQ_11 62
59 #define GPIO_S0_DED_IRQ_12 63
60 #define GPIO_S0_DED_IRQ_13 64
61 #define GPIO_S0_DED_IRQ_14 65
62 #define GPIO_S0_DED_IRQ_15 66
63 #define GPIO_S5_DED_IRQ_0 67
64 #define GPIO_S5_DED_IRQ_1 68
65 #define GPIO_S5_DED_IRQ_2 69
66 #define GPIO_S5_DED_IRQ_3 70
67 #define GPIO_S5_DED_IRQ_4 71
68 #define GPIO_S5_DED_IRQ_5 72
69 #define GPIO_S5_DED_IRQ_6 73
70 #define GPIO_S5_DED_IRQ_7 74
71 #define GPIO_S5_DED_IRQ_8 75
72 #define GPIO_S5_DED_IRQ_9 76
73 #define GPIO_S5_DED_IRQ_10 77
74 #define GPIO_S5_DED_IRQ_11 78
75 #define GPIO_S5_DED_IRQ_12 79
76 #define GPIO_S5_DED_IRQ_13 80
77 #define GPIO_S5_DED_IRQ_14 81
78 #define GPIO_S5_DED_IRQ_15 82
79 /* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */
80 #define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot
81 #define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot
82 #define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot)
83 #define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot)
85 #endif /* _BAYTRAIL_IRQ_H_ */