1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2016 Google, Inc
5 * From Coreboot src/soc/intel/broadwell/include/soc/gpio.h
8 #ifndef __ASM_ARCH_GPIO
9 #define __ASM_ARCH_GPIO
11 #define GPIO_PER_BANK 32
14 struct broadwell_bank_platdata {
16 const char *bank_name;
20 /* PCH-LP GPIOBASE Registers */
21 struct pch_lp_gpio_regs {
36 u32 gpi_route[GPIO_BANKS];
45 u32 rst_sel[GPIO_BANKS];
51 u32 gpi_is[GPIO_BANKS];
54 u32 gpi_ie[GPIO_BANKS];
62 } config[GPIO_BANKS * GPIO_PER_BANK];
64 check_member(pch_lp_gpio_regs, gpi_ie[0], 0x90);
65 check_member(pch_lp_gpio_regs, config[0], 0x100);
69 CONFA_MODE_GPIO = 1 << CONFA_MODE_SHIFT,
72 CONFA_DIR_INPUT = 1 << CONFA_DIR_SHIFT,
74 CONFA_INVERT_SHIFT = 3,
75 CONFA_INVERT = 1 << CONFA_INVERT_SHIFT,
77 CONFA_TRIGGER_SHIFT = 4,
78 CONFA_TRIGGER_LEVEL = 1 << CONFA_TRIGGER_SHIFT,
80 CONFA_LEVEL_SHIFT = 30,
81 CONFA_LEVEL_HIGH = 1UL << CONFA_LEVEL_SHIFT,
83 CONFA_OUTPUT_SHIFT = 31,
84 CONFA_OUTPUT_HIGH = 1UL << CONFA_OUTPUT_SHIFT,
86 CONFB_SENSE_SHIFT = 2,
87 CONFB_SENSE_DISABLE = 1 << CONFB_SENSE_SHIFT,